I2C Slave Mode; Figure 269. I2C Block Diagram - ST STM32F101 series Reference Manual

RM0008
SDA
SCL
SMBA
1. SMBA is an optional signal in SMBus mode. This signal is not applicable if SMBus is disabled.
2
26.3.2 I C slave mode
By default the I
Master mode a Start condition generation is needed.
The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
•
2 MHz in Sm mode
•
4 MHz in Fm mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
Figure 269. I
Data
control
Clock
control
Clock control
Register (CCR)
Control registers
(CR1&CR2)
Status registers
(SR1&SR2)
2
C interface operates in Slave mode. To switch from default Slave mode to
DocID13902 Rev 15
Inter-integrated circuit (I
2
C block diagram
Data register
Data shift register
Comparator
Own address register
Dual address register
PEC register
Control
logic
Interrupts DMA requests & ACK
2
C) interface
PEC calculation
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