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ST STM32F101xx Reference Manual

Advanced arm-based 32-bit mcus

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Download this manual See also: Programming Manual

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx

and STM32F107xx advanced ARM-based 32-bit MCUs

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F101xx, STM32F102xx, STM32F103xx and

STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,

STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as

STM32F10xxx throughout the document, unless otherwise specified.

The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the

low- and medium-density STM32F102xx datasheets and to the

STM32F105xx/STM32F107xx connectivity line datasheet.

For information on programming, erasing and protection of the internal Flash memory

please refer to:

●

RM0042, the Flash programming manual for low-, medium- high-density and

connectivity line STM32F10xxx devices

●

PM0068, the Flash programming manual for XL-density STM32F10xxx devices.

For information on the ARM Cortex™-M3 core, please refer to the STM32F10xxx Cortex™-

M3 programming manual (PM0056).

Related documents

Available from www.st.com:

■

STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and

datasheets

■

STM32F10xxx Cortex™-M3 programming manual (PM0056)

■

STM32F10xxx Flash programming manual (PM0042)

■

STM32F10xxx XL-density Flash programming manual (PM0068)

January 2011

Doc ID 13902 Rev 12

RM0008

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Summary of Contents for ST STM32F101xx

Page 1 The STM32F10xxx is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the STM32F105xx/STM32F107xx connectivity line datasheet.
Page 2: Table Of Contents
Contents RM0008 Contents Overview of the manual ........40 Documentation conventions .
Page 3 RM0008 Contents 5.2.2 Programmable voltage detector (PVD) ......68 Low-power modes ......... . 70 5.3.1 Slowing down system clocks .
Page 4 Contents RM0008 7.2.4 LSE clock ..........93 7.2.5 LSI clock .
Page 5 RM0008 Contents 8.3.1 Clock control register (RCC_CR) ......129 8.3.2 Clock configuration register (RCC_CFGR) ..... 131 8.3.3 Clock interrupt register (RCC_CIR) .
Page 6 Contents RM0008 9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 ..169 9.3.3 CAN1 alternate function remapping ......170 9.3.4 CAN2 alternate function remapping .
Page 7 RM0008 Contents 10.3.6 Pending register (EXTI_PR) ....... . 203 10.3.7 EXTI register map .
Page 8 Contents RM0008 11.12.2 ADC control register 1 (ADC_CR1) ......228 11.12.3 ADC control register 2 (ADC_CR2) ......230 11.12.4 ADC sample time register 1 (ADC_SMPR1) .
Page 9 RM0008 Contents 12.4.9 Simultaneous trigger with different LFSR generation ... . . 253 12.4.10 Simultaneous trigger with same triangle generation ....253 12.4.11 Simultaneous trigger with different triangle generation .
Page 10 Contents RM0008 13.4 DMA registers ..........273 13.4.1 DMA interrupt status register (DMA_ISR) .
Page 11 RM0008 Contents 14.4 TIM1&TIM8 registers ........321 14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) .
Page 12 Contents RM0008 15.3.11 Clearing the OCxREF signal on an external event ....372 15.3.12 Encoder interface mode ........373 15.3.13 Timer input XOR function .
Page 13 RM0008 Contents 16.4.5 Input capture mode ........418 16.4.6 PWM input mode (only for TIM9/12) .
Page 14 Contents RM0008 16.6.11 TIM10/11/13/14 register map ....... . 450 Basic timers (TIM6&TIM7) ........452 17.1 TIM6&TIM7 introduction .
Page 15 RM0008 Contents 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) ....474 18.4.7 RTC register map ......... 475 Independent watchdog (IWDG) .
Page 16 Contents RM0008 21.4.2 NAND/PC Card address mapping ......493 21.5 NOR Flash/PSRAM controller ....... . 494 21.5.1 External memory interface signals .
Page 17 RM0008 Contents 22.4.11 Card status register ........566 22.4.12 SD status register .
Page 18 Contents RM0008 22.9.12 SDIO interrupt clear register (SDIO_ICR) ..... . 592 22.9.13 SDIO mask register (SDIO_MASK) ......594 22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) .
Page 19 RM0008 Contents 24.5.1 Silent mode ..........635 24.5.2 Loop back mode .
Page 20 Contents RM0008 25.3.11 SPI interrupts ..........696 25.4 S functional description .
Page 21 RM0008 Contents 26.5 C debug mode ......... . . 747 26.6 C registers .
Page 22 Contents RM0008 27.6.2 Data register (USART_DR) ....... . . 794 27.6.3 Baud rate register (USART_BRR) .
Page 23 RM0008 Contents 28.11 Peripheral FIFO architecture ....... . . 820 28.11.1 Peripheral Rx FIFO .
Page 24 Contents RM0008 29.3 Ethernet pins ..........941 29.4 Ethernet functional description: SMI, MII and RMII .
Page 25 RM0008 Contents 30.1.1 Flash size register ........1045 30.2 Unique device ID register (96 bits) .
Page 26 Contents RM0008 31.15 ETM (Embedded trace macrocell) ......1067 31.15.1 General description ........1067 31.15.2 Signal protocol, packet types .
Page 27 RM0008 List of tables List of tables Table 1. Sections related to each STM32F10xxx product ....... . 40 Table 2.
Page 28 List of tables RM0008 Table 49. TIM11 remapping ............174 Table 50.
Page 29 RM0008 List of tables Table 100. External memory address ..........493 Table 101.
Page 30 List of tables RM0008 Table 152. Erase offset field ............573 Table 153.
Page 31 RM0008 List of tables Table 201. Data FIFO (DFIFO) access register map ........831 Table 202.
Page 32 List of figures RM0008 List of figures Figure 1. System architecture ............47 Figure 2.
Page 33 RM0008 List of figures Figure 49. DMA block diagram in low-, medium- high- and XL-density devices ....265 Figure 50. DMA1 request mapping ..........270 Figure 51.
Page 34 List of figures RM0008 Figure 99. Control circuit in external clock mode 2 + trigger mode ......320 Figure 100.
Page 35 RM0008 List of figures Figure 151. Counter timing diagram, internal clock divided by 2 ......413 Figure 152.
Page 36 List of figures RM0008 Figure 199. Asynchronous wait during a read access ........513 Figure 200.
Page 37 RM0008 List of figures discontinuous transfers ........... 690 Figure 246.
Page 38 List of figures RM0008 Figure 297. Hardware flow control between two USARTs ........789 Figure 298.
Page 39 RM0008 List of figures Figure 349. PTP trigger output to TIM2 ITR1 connection ........978 Figure 350.
Page 40: Overview Of The Manual
Overview of the manual RM0008 Overview of the manual Legend for Table • The section in each row applies to products in columns marked with “ " Table 1. Sections related to each STM32F10xxx product Section 2: • • • •...
Page 41 RM0008 Overview of the manual Table 1. Sections related to each STM32F10xxx product (continued) Section 12: Digital-to- • • • • analog converter (DAC) Section 14: Advanced- • • • • • • control timers (TIM1&TIM8) Section 15: General- • •...
Page 42 Overview of the manual RM0008 Table 1. Sections related to each STM32F10xxx product (continued) Section 26: Inter- • • • • • • • • • • integrated circuit (I2C) interface Section 27: Universal synchronous • • • • • •...
Page 43: Table 2. Sections Related To Each Peripheral
RM0008 Overview of the manual Legend for Table The section in this row must be read when using the peripherals in columns • • marked with “ " The section in this row can optionally be read when using the peripherals in ◊...
Page 44 Overview of the manual RM0008 Table 2. Sections related to each peripheral Section 11: Analog-to- • digital converter (ADC) Section 12: Digital-to- • analog converter (DAC) Section 14: Advanced- ◊ ◊ • control timers (TIM1&TIM8) Section 15: General- ◊ ◊ •...
Page 45 RM0008 Overview of the manual Table 2. Sections related to each peripheral Section 25: Serial • peripheral interface (SPI) Section 26: Inter- • integrated circuit (I2C) interface Section 27: Universal synchronous • asynchronous receiver transmitter (USART) Section 28: USB on- •...
Page 46: Documentation Conventions
Byte: data of 8-bit length. Peripheral availability For peripheral availability and number across all STM32F10xxx sales types, please refer to the low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the low- and medium-density STM32F102xx datasheets and to the connectivity line devices, STM32F105xx/STM32F107xx.
Page 47: Memory And Bus Architecture
RM0008 Memory and bus architecture Memory and bus architecture System architecture In low-, medium-, high- and XL-density devices, the main system consists of: ● Four masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) ●...
Page 48: Figure 2. System Architecture In Connectivity Line Devices
Memory and bus architecture RM0008 In connectivity line devices the main system consists of: ● Five masters: – Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA ● Three slaves: – Internal SRAM –...
Page 49: Memory Organization
RM0008 Memory and bus architecture DCode bus This bus connects the DCode bus (literal load and debug access) of the Cortex™-M3 core to the Flash memory Data interface. System bus This bus connects the system bus of the Cortex™-M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.
Page 50: Memory Map
Memory and bus architecture RM0008 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 3 gives the boundary addresses of the peripherals available in all STM32F10xxx devices. Table 3. Register boundary addresses Boundary address Peripheral Register map...
Page 51 RM0008 Memory and bus architecture Table 3. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4001 5800 - 0x4001 7FFF Reserved 0x4001 5400 - 0x4001 57FF TIM11 timer Section 16.5.14 on page 441 0x4001 5000 - 0x4001 53FF TIM10 timer Section 16.5.14 on page 441 0x4001 4C00 - 0x4001 4FFF TIM9 timer...
Page 52 Memory and bus architecture RM0008 Table 3. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF Section 12.5.14 on page 262 0x4000 7000 - 0x4000 73FF Power control PWR Section 5.4.3 on page 78 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP)
Page 53: Embedded Sram
RM0008 Memory and bus architecture 3.3.1 Embedded SRAM The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000. 3.3.2 Bit banding The Cortex™-M3 memory map includes two bit-band regions.
Page 54: Embedded Flash Memory
Memory and bus architecture RM0008 3.3.3 Embedded Flash memory The high-performance Flash memory module has the following key features: ● For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read- while-write (RWW) capability: – bank 1: fixed size of 512 Kbytes –...
Page 55: Table 5. Flash Module Organization (Medium-Density Devices)
RM0008 Memory and bus architecture Table 4. Flash module organization (low-density devices) (continued) Block Name Base addresses Size (bytes) System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes Information block Option Bytes 0x1FFF F800 - 0x1FFF F80F FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR...
Page 56: Table 6. Flash Module Organization (High-Density Devices)
Memory and bus architecture RM0008 Table 6. Flash module organization (high-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes Page 3 0x0800 1800 - 0x0800 1FFF...
Page 57: Table 7. Flash Module Organization (Connectivity Line Devices)
RM0008 Memory and bus architecture Table 7. Flash module organization (connectivity line devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes Page 3 0x0800 1800 - 0x0800 1FFF...
Page 58 Memory and bus architecture RM0008 Table 8. XL-density Flash module organization (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B FLASH_SR 0x4002 200C - 0x4002 200F FLASH_CR 0x4002 2010 - 0x4002 2013 FLASH_AR...
Page 59 RM0008 Memory and bus architecture Note: These options should be used in accordance with the Flash memory access time. The wait states represent the ratio of the SYSCLK (system clock) period to the Flash memory access time: ≤ zero wait state, if 0 < SYSCLK 24 MHz ≤...
Page 60: Boot Configuration
Memory and bus architecture RM0008 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030 Reserved PRFTBS PRFTBE HLFCYA LATENCY Reserved Bits 31:6 Reserved, must be kept cleared. Bit 5 PRFTBS: Prefetch buffer status This bit provides the status of the prefetch buffer. 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled Bit 4 PRFTBE: Prefetch buffer enable...
Page 61 Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces: ●...
Page 62: Crc Calculation Unit
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 63: Crc Functional Description
RM0008 CRC calculation unit CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: ● is used as an input register to enter new data in the CRC calculator (when writing into the register) ●...
Page 64: Control Register (Crc_Cr)
CRC calculation unit RM0008 Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register. 4.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000...
Page 65: Power Control (Pwr)
Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F101xx family, unless otherwise specified. Power supplies The device requires a 2.0-to-3.6 V operating voltage supply (V ).
Page 66: Independent A/D And D/A Converter Supply And Reference Voltage
Power control (PWR) RM0008 Figure 4. Power supply overview domain REF- A/D converter (from 2.4 V up to V D/A converter REF+ Temp. sensor Reset block domain 1.8 V domain I/O Ring Core Memories Standby circuitry digital (Wakeup logic, peripherals IWDG) Voltage Regulator Low voltage detector...
Page 67: Battery Backup Domain
RM0008 Power control (PWR) 5.1.2 Battery backup domain To retain the content of the Backup registers and supply the RTC function when V turned off, V pin can be connected to an optional standby voltage supplied by a battery or by another source.
Page 68: Voltage Regulator
Power control (PWR) RM0008 5.1.3 Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. ● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals).
Page 69: Figure 6. Pvd Thresholds
RM0008 Power control (PWR) PVD output interrupt can be generated when V drops below the PVD threshold and/or when V rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.
Page 70: Low-Power Modes
Power control (PWR) RM0008 Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 71: Peripheral Clock Gating
RM0008 Power control (PWR) 5.3.2 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 72: Stop Mode
Power control (PWR) RM0008 Table 12. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 0 Refer to the Cortex™-M3 System Control register. If WFI was used for entry: Interrupt: Refer to Table 63: Vector table for other STM32F10xxx devices Mode exit...
Page 73: Standby Mode
RM0008 Power control (PWR) ● real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) ● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). ●...
Page 74: Table 15. Standby Mode
Power control (PWR) RM0008 Entering Standby mode Refer to Table 15 for more details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: ● Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option.
Page 75: Auto-Wakeup (Awu) From Low-Power Mode
RM0008 Power control (PWR) Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex™-M3 core is no longer clocked.
Page 76 Power control (PWR) RM0008 Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
Page 77: Power Control/Status Register (Pwr_Csr)
RM0008 Power control (PWR) 5.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Reserved EWUP PVDO Reserved Reserved Bits 31:9 Reserved, always read as 0.
Page 78: Pwr Register Map
Power control (PWR) RM0008 5.4.3 PWR register map The following table summarizes the PWR registers. Table 16. PWR register map and reset values Offset Register PWR_CR PLS[2:0] 0x000 Reserved Reset value PWR_CSR 0x004 Reserved Reserved Reset value Refer to Table 3 on page 50 for the register boundary addresses.
Page 79: Backup Registers (Bkp)
Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to the whole STM32F101xx family, unless otherwise specified. BKP introduction The backup registers are forty two 16-bit registers for storing 84 bytes of user application data.
Page 80: Bkp Functional Description
The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits. For more details about RTC calibration and how to use it to improve timekeeping accuracy, please refer to AN2604 "STM32F101xx and STM32F103xx RTC calibration”. 80/1096...
Page 81: Bkp Registers
RM0008 Backup registers (BKP) BKP registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 D[15:0]...
Page 82: Backup Control Register (Bkp_Cr)
Backup registers (BKP) RM0008 Bit 6:0 CAL[6:0]: Calibration value This value indicates the number of clock pulses that will be ignored every 2^20 clock pulses. This allows the calibration of the RTC, slowing down the clock by steps of 1000000/2^20 PPM.
Page 83: Bkp Register Map
RM0008 Backup registers (BKP) Bit 8 TEF: Tamper event flag This bit is set by hardware when a Tamper event is detected. It is cleared by writing 1 to the CTE bit. 0: No Tamper event 1: A Tamper event occurred Note: A Tamper event resets all the BKP_DRx registers.
Page 84 Backup registers (BKP) RM0008 Table 17. BKP register map and reset values (continued) Offset Register BKP_DR7 D[15:0] 0x1C Reserved Reset value BKP_DR8 D[15:0] 0x20 Reserved Reset value BKP_DR9 D[15:0] 0x24 Reserved Reset value BKP_DR10 D[15:0] 0x28 Reserved Reset value BKP_RTCCR CAL[6:0] Reserved Reset value...
Page 85 RM0008 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register BKP_DR20 D[15:0] 0x64 Reserved Reset value BKP_DR21 D[15:0] 0x68 Reserved Reset value BKP_DR22 D[15:0] 0x6C Reserved Reset value BKP_DR23 D[15:0] 0x70 Reserved Reset value BKP_DR24 D[15:0] 0x74 Reserved...
Page 86 Backup registers (BKP) RM0008 Table 17. BKP register map and reset values (continued) Offset Register BKP_DR37 D[15:0] 0xA8 Reserved Reset value BKP_DR38 D[15:0] 0xAC Reserved Reset value 0xB0 BKP_DR39 D[15:0] Reserved Reset value BKP_DR40 D[15:0] 0xB4 Reserved Reset value 0xB8 BKP_DR41 D[15:0] Reserved...
Page 87: Low-, Medium-, High- And Xl-Density Reset And Clock Control (Rcc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 88: Power Reset
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
Page 89: Clocks
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Clocks Three different clock sources can be used to drive the system clock (SYSCLK): ● HSI oscillator clock ● HSE oscillator clock ● PLL clock The devices have the following two secondary clock sources: ●...
Page 90: Figure 8. Clock Tree
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Figure 8. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics”...
Page 91: Hse Clock
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) The timer clock frequencies are automatically fixed by hardware. There are two cases: if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
Page 92: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 93: Lse Clock
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL enabled, these parameters cannot be changed.
Page 94: System Clock (Sysclk) Selection
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 oscillator, the software can adjust the programmable 20-bit prescaler of the RTC to get an accurate time base or can compute accurate IWDG timeout. Use the following procedure to calibrate the LSI: Enable TIM5 timer and configure channel4 in input capture mode Set the TIM5CH4_IREMAP bit in the AFIO_MAPR register to connect the LSI clock internally to TIM5 channel4 input capture for calibration purpose.
Page 95: Watchdog Clock
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. Consequently: ● If LSE is selected as RTC clock: – The RTC continues to work even if the V supply is switched off, provided the supply is maintained.
Page 96: Rcc Registers
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 RCC registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. 7.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLON Reserved...
Page 97 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 16 HSEON: External high-speed clock enable Set and cleared by software. Cleared by hardware to stop the external 1-25MHz oscillator when entering in Stop or Standby mode. This bit cannot be reset if the external 4-16 MHz oscillator is used directly or indirectly as the system clock or is selected to become the system clock.
Page 98: Clock Configuration Register (Rcc_Cfgr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. MCO[2:0] PLLMUL[3:0] XTPRE...
Page 99 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4...
Page 100 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bits 10:8 PPRE1: APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4...
Page 101: Clock Interrupt Register (Rcc_Cir)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access CSSC RDYC RDYC RDYC RDYC RDYC Reserved Reserved CSSF RDYIE RDYIE...
Page 102 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 12 PLLRDYIE: PLL ready interrupt enable Set and cleared by software to enable/disable interrupt caused by PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz oscillator stabilization.
Page 103: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 1 LSERDYF: LSE ready interrupt flag Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is set. Cleared by software setting the LSERDYC bit. 0: No clock ready interrupt caused by the external 32 kHz oscillator 1: Clock ready interrupt caused by the external 32 kHz oscillator Bit 0 LSIRDYF: LSI ready interrupt flag...
Page 104 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 ADC1RST: ADC1 interface reset Set and cleared by software. 0: No effect 1: Reset ADC1 interface Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software.
Page 105 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 2 IOPARST: IO port A reset...
Page 106: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access UART UART USART USART I2C2 I2C1 Reserved Res.
Page 107 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bit 20 UART5RST: USART5 reset Set and cleared by software. 0: No effect 1: Reset USART5 Bit 19 UART4RST: USART4 reset Set and cleared by software.
Page 108: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 6 TIM12RST: TIM12 timer reset Set and cleared by software. 0: No effect 1: Reset TIM12 Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software.
Page 109: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 10 SDIOEN: SDIO clock enable Set and cleared by software. 0: SDIO clock disabled 1: SDIO clock enabled Bits 9 Reserved, always read as 0. Bit 8 FSMCEN: FSMC clock enable Set and cleared by software.
Page 110 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 TIM11 TIM10 TIM9 Reserved Reserved ADC3 TIM8 SPI1 TIM1 ADC2 ADC1 IOPG IOPF IOPE IOPD IOPC IOPB IOPA AFIO USAR T1EN Res. Bits 31:22 Reserved, always read as 0. Bit 21 TIM11EN: TIM11 timer clock enable Set and cleared by software.
Page 111: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software.
Page 112 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished.
Page 113 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 UART5EN: USART5 clock enable Set and cleared by software. 0: USART5 clock disabled 1: USART5 clock enabled Bit 19 UART4EN: USART4 clock enable...
Page 114 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 6 TIM12EN: TIM12 timer clock enable Set and cleared by software. 0: TIM12 clock disabled 1: TIM12 clock enabled Bit 5 TIM7EN: TIM7 timer clock enable Set and cleared by software. 0: TIM7 clock disabled 1: TIM7 clock enabled Bit 4 TIM6EN: TIM6 timer clock enable...
Page 115: Backup Domain Control Register (Rcc_Bdcr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.9 Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 116 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 1 LSERDY: External low-speed oscillator ready Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock cycles.
Page 117: Control/Status Register (Rcc_Csr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 118 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 26 PINRSTF: PIN reset flag Set by hardware when a reset from the NRST pin occurs. Cleared by writing to the RMVF bit. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 Reserved, always read as 0.
Page 119: Rcc Register Map
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.11 RCC register map The following table gives the RCC register map and the reset values. Table 18. RCC register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x00 Reserved Reserved...
Page 120: Connectivity Line Devices: Reset And Clock Control (Rcc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 121: Power Reset
RM0008 Connectivity line devices: reset and clock control (RCC) Low-power management reset There are two ways to generate a low-power management reset: Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
Page 122: Backup Domain Reset
Connectivity line devices: reset and clock control (RCC) RM0008 8.1.3 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the Backup domain control register...
Page 123: Figure 11. Clock Tree
RM0008 Connectivity line devices: reset and clock control (RCC) Figure 11. Clock tree 40 kHz to independent watchdog IWDGCLK to RTC OSC32_IN 32.768 kHz RTCCLK OSC32_OUT /128 RTCSEL[1:0] FLITFCLK to Flash prog. IF XT1 to MCO 8 MHz SYSCLK HSI RC PLLMUL system clock 3-25 MHz...
Page 124: Hse Clock
Connectivity line devices: reset and clock control (RCC) RM0008 Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz.
Page 125: Hsi Clock
RM0008 Connectivity line devices: reset and clock control (RCC) Figure 12. HSE/ LSE clock sources Clock source Hardware configuration OSC_OUT External clock (HiZ) External source OSC_IN OSC_OUT Crystal/ceramic resonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 50 MHz.
Page 126: Plls
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 127: Lsi Clock
RM0008 Connectivity line devices: reset and clock control (RCC) External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR).
Page 128: Clock Security System (Css)
Connectivity line devices: reset and clock control (RCC) RM0008 8.2.7 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System...
Page 129: Clock-Out Capability
RM0008 Connectivity line devices: reset and clock control (RCC) 8.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock.
Page 130 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 0: PLL2 unlocked 1: PLL2 locked Bit 26 PLL2ON: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode.
Page 131: Clock Configuration Register (Rcc_Cfgr)
RM0008 Connectivity line devices: reset and clock control (RCC) Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.
Page 132 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL clock divided by 2 selected 1000: PLL2 clock selected 1001: PLL3 clock divided by 2 selected 1010: XT1 external 3-25 MHz oscillator clock selected (for Ethernet)
Page 133 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 14:14 ADCPRE[1:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADCs. 00: PCLK2 divided by 2 01: PCLK2 divided by 4 10: PCLK2 divided by 6 11: PCLK2 divided by 8 Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) Set and cleared by software to control the division factor of the APB High speed clock (PCLK2).
Page 134: Clock Interrupt Register (Rcc_Cir)
Connectivity line devices: reset and clock control (RCC) RM0008 Bits 1:0 SW[1:0]: System clock Switch Set and cleared by software to select SYSCLK source. Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled).
Page 135 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 18 HSIRDYC: HSI ready interrupt clear This bit is set by software to clear the HSIRDYF flag. 0: No effect 1: Clear HSIRDYF flag Bit 17 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag.
Page 136 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 7 CSSF: Clock security system interrupt flag Set by hardware when a failure is detected in the external 3-25 MHz oscillator. It is cleared by software setting the CSSC bit. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 6 PLL3RDYF: PLL3 Ready Interrupt flag...
Page 137: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Reserved USART1 SPI1 TIM1 ADC2 ADC1 IOPE IOPD IOPC IOPB IOPA AFIO...
Page 138: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
Connectivity line devices: reset and clock control (RCC) RM0008 Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 2 IOPARST: I/O port A reset...
Page 139 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 27 BKPRST: Backup interface reset Set and cleared by software. 0: No effect 1: Reset backup interface Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: No effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software.
Page 140 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 13:12 Reserved, always read as 0. Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, always read as 0. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software.
Page 141: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access MACR Reserved ETHM SRAM DMA2 DMA1 ETHM OTGF FLITFE ACTX CRCEN...
Page 142: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Connectivity line devices: reset and clock control (RCC) RM0008 Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, always read as 0.
Page 143 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable...
Page 144: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
Connectivity line devices: reset and clock control (RCC) RM0008 8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going.
Page 145 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable...
Page 146: Backup Domain Control Register (Rcc_Bdcr)
Connectivity line devices: reset and clock control (RCC) RM0008 Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable...
Page 147 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 15 RTCEN: RTC clock enable Set and cleared by software. 0: RTC clock disabled 1: RTC clock enabled Bits 14:10 Reserved, always read as 0. Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC.
Page 148: Control/Status Register (Rcc_Csr)
Connectivity line devices: reset and clock control (RCC) RM0008 8.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register.
Page 149: Ahb Peripheral Clock Reset Register (Rcc_Ahbrstr)
RM0008 Connectivity line devices: reset and clock control (RCC) Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, always read as 0. Bit 1 LSIRDY: Internal low speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
Page 150: Clock Configuration Register2 (Rcc_Cfgr2)
Connectivity line devices: reset and clock control (RCC) RM0008 8.3.12 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access I2S3S I2S2S PREDI V1SRC Reserved PLL3MUL[3:0] PLL2MUL[3:0] PREDIV2[3:0] PREDIV1[3:0] Bits 31:19 Reserved, always read as 0. Bit 18 I2S3SRC: I2S3 clock source Set and cleared by software to select I2S3 clock source.
Page 151 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock entry x 9 1000: PLL2 clock entry x 10 1001: PLL2 clock entry x 11...
Page 152: Rcc Register Map
Connectivity line devices: reset and clock control (RCC) RM0008 Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled. Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly.
Page 153 RM0008 Connectivity line devices: reset and clock control (RCC) Table 19. RCC register map and reset values (continued) Offset Register RCC_AHBENR 0x014 Reserved Reserved Reset value 0x018 RCC_APB2ENR Reserved Reset value RCC_APB1ENR Reser 0x01C Reserved Reset value RCC_BDCR 0x020 Reserved Reserved Reserved [1:0]...
Page 154: General-Purpose And Alternate-Function I/Os (Gpios And Afios)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 155: Figure 13. Basic Structure Of A Standard I/O Port Bit
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 13. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral on/off Alternate Function Input on/off Read TTL Schmitt Protection trigger on/off diode Input driver I/O pin Write Output driver Protection diode...
Page 156: General-Purpose I/O (Gpio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 20. Port bit configuration table PxODR Configuration mode CNF1 CNF0 MODE1 MODE0 register Push-pull 0 or 1 General purpose output Open-drain 0 or 1 Push-pull don’t care Alternate Function Table 21 output Open-drain don’t care...
Page 157: External Interrupt/Wakeup Lines
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) or for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be modified. 9.1.3 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.
Page 158: Input Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.1.7 Input configuration When the I/O Port is programmed as Input: ● The Output Buffer is disabled ● The Schmitt Trigger Input is activated ● The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): ●...
Page 159: Alternate Function Configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 16 on page 159 shows the Output configuration of the I/O Port bit. Figure 16. Output configuration Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Output driver Protection diode...
Page 160: Analog Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Figure 17. Alternate function configuration Alternate Function Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Input driver I/O pin Write Output driver Protection diode P-MOS Output control N-MOS Read/write push-pull or...
Page 161: Gpio Configurations For Device Peripherals
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 18. High impedance-analog configuration Analog Input To on-chip peripheral Read or V DD_FT TTL Schmitt Protection trigger diode Write Input driver I/O pin Protection diode Read/write From on-chip peripheral ai14786 9.1.11 GPIO configurations for device peripherals Table 22 Table 33...
Page 162: Table 25. Spi
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 24. USARTs (continued) USART pinout Configuration GPIO configuration Full duplex Input floating / Input pull-up USARTx_RX Half duplex synchronous mode Not used. Can be used as a general IO USARTx_CK Synchronous mode Alternate function push-pull USARTx_RTS Hardware flow control...
Page 163: Table 27. I2C
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 27. I2C pinout Configuration GPIO configuration I2Cx_SCL I2C clock Alternate function open drain I2Cx_SDA I2C Data I/O Alternate function open drain Table 28. BxCAN BxCAN pinout GPIO configuration CAN_TX (Transmit data line) Alternate function push-pull CAN_RX (Receive data line) Input floating / Input pull-up...
Page 164: Sdio
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 31. SDIO SDIO pinout GPIO configuration SDIO_CK Alternate function push-pull SDIO_CMD Alternate function push-pull SDIO[D7:D0] Alternate function push-pull The GPIO configuration of the ADC inputs should be analog. Figure 19. ADC / DAC ADC/DAC pin GPIO configuration ADC/DAC...
Page 165: Gpio Registers
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0]...
Page 166: Port Configuration Register High (Gpiox_Crh) (X=A..g
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 ..
Page 167: Port Output Data Register (Gpiox_Odr) (X=A
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 Reserved ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Bits 31:16 Reserved, always read as 0.
Page 168: Port Bit Reset Register (Gpiox_Brr) (X=A
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 Reserved BR15 BR14 BR13 BR12 BR11 BR10 Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only.
Page 169: Alternate Function I/O And Debug Configuration (Afio)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. GPIOx_LCKR register is locked until an MCU reset occurs.
Page 170: Can1 Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.3.3 CAN1 alternate function remapping The CAN signals can be mapped on Port A, Port B or Port D as shown in Table 34. For port D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages. Table 34.
Page 171: Adc Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR). Refer to Table 37 Table 37.
Page 172: Timer Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 41. ADC2 external trigger regular conversion alternate function remapping Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1 ADC2 external trigger regular ADC2 external trigger regular ADC2 external trigger regular conversion is connected to conversion is connected to conversion EXTI11...
Page 173: Table 46. Tim1 Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 45. TIM2 alternate function remapping TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: Alternate function 0] = “00” (no 0] = “01” (partial 0] = “10” (partial 0] = “11” (full remap) remap) remap) remap) TIM2_CH1_ETR PA15 PA15...
Page 174: Usart Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 49. TIM11 remapping Alternate function TIM11_REMAP = 0 TIM11_REMAP = 1 TIM11_CH1 1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2).
Page 175: I2C1 Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 54. USART1 remapping Alternate function USART1_REMAP = 0 USART1_REMAP = 1 USART1_TX USART1_RX PA10 9.3.9 I2C1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 55. I2C1 remapping Alternate function I2C1_REMAP = 0...
Page 176: Afio Registers
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 58. ETH remapping Alternate function ETH_REMAP = 0 ETH_REMAP = 1 RX_DV-CRS_DV RXD0 RXD1 PD10 RXD2 PD11 RXD3 PD12 AFIO registers Refer to Section 2.1 on page 46for a list of abbreviations used in register descriptions. Note: To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock should first be enabled.
Page 177: Event Control Register (Afio_Evcr)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.4.1 Event control register (AFIO_EVCR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved EVOE PORT[2:0] PIN[3:0] Reserved Bits 31:8 Reserved Bit 7 EVOE: Event output enable Set and cleared by software. When set the EVENTOUT Cortex output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits.
Page 178: Af Remap And Debug I/O Configuration Register (Afio_Mapr)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 Memory map and bit definitions for low-, medium- high- and XL-density devices: ADC2_ ADC1_ ADC2_ET ADC1_ET TIM5CH SWJ_ ETRGR...
Page 179 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger injected conversion. When reset the ADC1 External trigger injected conversion is connected to EXTI15.
Page 180 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,...
Page 181 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Memory map and bit definitions for connectivity line devices: PTP_P TIM2ITR TIM5CH SPI3_ SWJ_ MII_RMI CAN2_ ETH_R PS_RE 4_IREM REMAP CFG[2:0] I_SEL REMAP EMAP Res. Res. Reserved IREMAP PD01_ CAN1_REMAP TIM4_ TIM3_REMAP TIM2_REMAP TIM1_REMAP USART3_...
Page 182 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bit 22 CAN2_REMAP: CAN2 I/O remapping This bit is set and cleared by software. It controls the CAN2_TX and CAN2_RX pins. 0: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 1: Remap (CAN2_RX/PB5, CAN2_TX/PB6) Note: This bit is available only in connectivity line devices and is reserved otherwise. Bit 21 ETH_REMAP: Ethernet MAC I/O remapping This bit is set and cleared by software.
Page 183 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 9:8 TIM2_REMAP[1:0]: TIM2 remapping These bits are set and cleared by software. They control the mapping of TIM2 channels 1 to 4 and external trigger (ETR) on the GPIO ports. 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
Page 184: External Interrupt Configuration Register 1 (Afio_Exticr1)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) Address offset: 0x08 Reset value: 0x0000 Reserved EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3) These bits are written by software to select the source input for EXTIx external interrupt. Refer to Section 10.2.5: External interrupt/event line mapping on page 199 0000: PA[x] pin...
Page 185: External Interrupt Configuration Register 3 (Afio_Exticr3)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 Reserved EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 186: Af Remap And Debug I/O Configuration Register2 (Afio_Mapr2)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) Address offset: 0x1C Reset value: 0x0000 0000 Reserved FSMC_ TIM14_ TIM13_ TIM11_ TIM10_ TIM9_R NADV REMAP REMAP REMAP REMAP EMAP Reserved Reserved Bits 31:11 Reserved.
Page 187: Gpio And Afio Register Maps
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO and AFIO register maps Refer to Table 3 on page 50 for the register boundary addresses. The following tables give the GPIO and AFIO register map and the reset values. Table 59. GPIO register map and reset values Offset Register CNF7...
Page 188 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 60. AFIO register map and reset values (continued) Offset Register AFIO_EXTICR3 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] 0x10 Reserved Reset value AFIO_EXTICR4 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0x14 Reserved Reset value AFIO_MAPR2 0x1C Reserved Reserved Reset value Refer to...
Page 189: Interrupts And Events
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 190 Interrupts and events RM0008 Table 61. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority Non maskable interrupt. The RCC fixed Clock Security System (CSS) is 0x0000_0008 linked to the NMI vector. fixed HardFault All class of fault 0x0000_000C settable MemManage...
Page 191 RM0008 Interrupts and events Table 61. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority settable CAN1_TX CAN1 TX interrupts 0x0000_008C settable CAN1_RX0 CAN1 RX0 interrupts 0x0000_0090 settable CAN1_RX1 CAN1 RX1 interrupt 0x0000_0094 settable CAN1_SCE CAN1 SCE interrupt 0x0000_0098 settable EXTI9_5...
Page 192: Table 62. Vector Table For Xl-Density Devices
Interrupts and events RM0008 Table 61. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority settable DMA2_Channel1 DMA2 Channel1 global interrupt 0x0000_0120 settable DMA2_Channel2 DMA2 Channel2 global interrupt 0x0000_0124 settable DMA2_Channel3 DMA2 Channel3 global interrupt 0x0000_0128 settable DMA2_Channel4 DMA2 Channel4 global interrupt...
Page 193 RM0008 Interrupts and events Table 62. Vector table for XL-density devices (continued) Type of Acronym Description Address priority PVD through EXTI Line detection settable PVD 0x0000_0044 interrupt settable TAMPER Tamper interrupt 0x0000_0048 10 settable RTC RTC global interrupt 0x0000_004C 11 settable FLASH Flash global interrupt 0x0000_0050 12 settable RCC...
Page 194 Interrupts and events RM0008 Table 62. Vector table for XL-density devices (continued) Type of Acronym Description Address priority 31 38 settable I2C1_EV I2C1 event interrupt 0x0000_00BC 32 39 settable I2C1_ER I2C1 error interrupt 0x0000_00C0 33 40 settable I2C2_EV I2C2 event interrupt 0x0000_00C4 34 41 settable I2C2_ER I2C2 error interrupt...
Page 195: Table 63. Vector Table For Other Stm32F10Xxx Devices
RM0008 Interrupts and events Table 63. Vector table for other STM32F10xxx devices Type of Acronym Description Address priority Reserved 0x0000_0000 fixed Reset Reset 0x0000_0004 Non maskable interrupt. The RCC fixed Clock Security System (CSS) is 0x0000_0008 linked to the NMI vector. fixed HardFault All class of fault...
Page 196 Interrupts and events RM0008 Table 63. Vector table for other STM32F10xxx devices (continued) Type of Acronym Description Address priority settable DMA1_Channel7 DMA1 Channel7 global interrupt 0x0000_0084 settable ADC1_2 ADC1 and ADC2 global interrupt 0x0000_0088 USB_HP_CAN_ USB High Priority or CAN TX settable 0x0000_008C interrupts...
Page 197: External Interrupt/Event Controller (Exti)
RM0008 Interrupts and events Table 63. Vector table for other STM32F10xxx devices (continued) Type of Acronym Description Address priority settable ADC3 ADC3 global interrupt 0x0000_00FC settable FSMC FSMC global interrupt 0x0000_0100 settable SDIO SDIO global interrupt 0x0000_0104 settable TIM5 TIM5 global interrupt 0x0000_0108 settable SPI3...
Page 198: Wakeup Event Management
Interrupts and events RM0008 Figure 20. External interrupt/event controller block diagram AMBA APB bus PCLK2 Peripheral interface Rising Falling Software Interrupt Pending trigger trigger interrupt mask request selection selection event register register register register register To NVIC Interrupt Controller Edge detect Pulse Input circuit...
Page 199: External Interrupt/Event Line Mapping
RM0008 Interrupts and events event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set An interrupt/event request can also be generated by software by writing a ‘1’...
Page 200: Figure 21. External Interrupt/Event Gpio Mapping
Interrupts and events RM0008 Figure 21. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15 PB15 PC15 EXTI15 PD15 PE15 PF15 PG15 1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO clock should first be enabled.
Page 201: Exti Registers
RM0008 Interrupts and events 10.3 registers EXTI Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR19 MR18...
Page 202: Rising Trigger Selection Register (Exti_Rtsr)
Interrupts and events RM0008 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR19 TR18 TR17 TR16 Reserved TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
Page 203: Software Interrupt Event Register (Exti_Swier)
RM0008 Interrupts and events 10.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:20 Reserved, must be kept at reset value (0).
Page 204: Exti Register Map
Interrupts and events RM0008 10.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Table 64. External interrupt/event controller register map and reset values Offset Register EXTI_IMR...
Page 205: Analog-To-Digital Converter (Adc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 206: Adc Main Features
STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz) – STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz) – STM32F102xx USB access line devices: 1.2 µs at 48 MHz –...
Page 207: Figure 22. Single Adc Block Diagram
RM0008 Analog-to-digital converter (ADC) Figure 22. Single ADC block diagram Interrupt Flags enable bits End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion JEOC JEOCIE Analog watchdog event AWDIE Analog watchdog Compare Result High Threshold (12 bits) Low Threshold (12 bits) Injected data registers REF+...
Page 208: Table 65. Adc Pins
Analog-to-digital converter (ADC) RM0008 Table 65. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, ≤ ≤ REF+ positive 2.4 V REF+ Analog power supply equal to V Input, analog supply ≤ ≤ 2.4 V 3.6 V Input, analog reference...
Page 209: Adc On-Off Control
RM0008 Analog-to-digital converter (ADC) 11.3.1 ADC on-off control The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from Power Down mode. Conversion starts when ADON bit is set for a second time by software after ADC power-up time (t STAB...
Page 210: Continuous Conversion Mode
Analog-to-digital converter (ADC) RM0008 Once the conversion of the selected channel is complete: ● If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set –...
Page 211: Analog Watchdog
RM0008 Analog-to-digital converter (ADC) 11.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register.
Page 212: Injected Channel Management
It is not possible to use both auto-injected and discontinuous modes simultaneously. Figure 25. Injected conversion latency ADC clock Inj. event Reset ADC max latency 1. The maximum latency value can be found in the electrical characteristics of the STM32F101xx and STM32F103xx datasheets. 212/1096 Doc ID 13902 Rev 12...
Page 213: Discontinuous Mode
RM0008 Analog-to-digital converter (ADC) 11.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers.
Page 214: Data Alignment
Analog-to-digital converter (ADC) RM0008 Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed. It is recommended to calibrate the ADC once at power-on. The calibration codes are stored in the ADC_DR as soon as the calibration phase ends.
Page 215: Channel-By-Channel Programmable Sample Time
RM0008 Analog-to-digital converter (ADC) 11.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us- ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time. The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 cycles Example:...
Page 216: Table 68. External Trigger For Injected Channels For Adc1 And Adc2
Analog-to-digital converter (ADC) RM0008 Table 68. External trigger for injected channels for ADC1 and ADC2 Source Connection type JEXTSEL[2:0] TIM1_TRGO event TIM1_CC4 event TIM2_TRGO event Internal signal from on-chip timers TIM2_CC1 event TIM3_CC4 event TIM4_TRGO event EXTI line 15/TIM8_CC4 External pin/Internal signal from (1)(2) event on-chip timers...
Page 217: Dma Request
RM0008 Analog-to-digital converter (ADC) The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger. 11.8 DMA request Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel.
Page 218: Dual Adc Mode
Analog-to-digital converter (ADC) RM0008 11.9 Dual ADC mode In devices with two ADCs or more, dual ADC mode can be used (see Figure 29). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register.
Page 219: Figure 29. Dual Adc Block Diagram
RM0008 Analog-to-digital converter (ADC) Figure 29. Dual ADC block diagram Regular data register (12 bits) (16 bits) Injected data registers (4 x 16 bits) Regular ADC2 (Slave) channels injected channels internal triggers Regular data register (16 bits) Injected data registers (4 x 16 bits) ADCx_IN0 Regular...
Page 220: Injected Simultaneous Mode
Analog-to-digital converter (ADC) RM0008 11.9.1 Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits ADC1_CR2 in the register). A simultaneous trigger is provided to ADC2. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).
Page 221: Fast Interleaved Mode
RM0008 Analog-to-digital converter (ADC) Figure 31. Regular simultaneous mode on 16 channels Sampling Conversion ADC1 CH15 ADC2 CH15 CH14 CH13 CH12 End of conversion on ADC1 and ADC2 Trigger 11.9.3 Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1.
Page 222: Alternate Trigger Mode
Analog-to-digital converter (ADC) RM0008 After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword.
Page 223: Independent Mode
RM0008 Analog-to-digital converter (ADC) If the injected discontinuous mode is enabled for both ADC1 and ADC2: ● When the 1st trigger occurs, the first injected channel in ADC1 is converted. ● When the 2nd trigger arrives, the first injected channel in ADC2 are converted ●...
Page 224: Combined Injected Simultaneous + Interleaved
Analog-to-digital converter (ADC) RM0008 Figure 36. Alternate + Regular simultaneous 1st trig ADC1 reg ADC1 inj ADC2 reg ADC2 inj synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored.
Page 225: Temperature Sensor
RM0008 Analog-to-digital converter (ADC) 11.10 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs.
Page 226: Adc Interrupts
Analog-to-digital converter (ADC) RM0008 Reading the temperature To use the sensor: Select the ADCx_IN16 input channel. Select a sample time of 17.1 µs Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. Start the ADC conversion by setting the ADON bit (or by external trigger).
Page 227: Adc Registers
RM0008 Analog-to-digital converter (ADC) 11.12 ADC registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved STRT...
Page 228: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0008 11.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 AWDEN JAWDEN DUALMOD[3:0] Reserved Reserved JDISCE DISC DISCNUM[2:0] JAUTO SCAN JEOC IE AWDIE EOCIE AWDCH[4:0] Bits 31:24 Reserved, must be kept cleared. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software.
Page 229 RM0008 Analog-to-digital converter (ADC) Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels.
Page 230: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0008 Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits These bits are set and cleared by software. They select the input channel to be guarded by the Analog watchdog. 00000: ADC analog Channel0 00001: ADC analog Channel1 ..
Page 231 RM0008 Analog-to-digital converter (ADC) Bit 20 EXTTRIG: External trigger conversion mode for regular channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of a regular channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 19:17 EXTSEL[2:0]: External event select for regular group These bits select the external event used to trigger the start of conversion of a regular group:...
Page 232 Analog-to-digital converter (ADC) RM0008 Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected group: For ADC1 and ADC2 the assigned triggers are: 000: Timer 1 TRGO event 001: Timer 1 CC4 event 010: Timer 2 TRGO event 011: Timer 2 CC1 event...
Page 233 RM0008 Analog-to-digital converter (ADC) Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset. 0: Single conversion mode 1: Continuous conversion mode Bit 0 ADON: A/D converter ON / OFF This bit is set and cleared by software.
Page 234: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0008 11.12.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 SMP17[2:0] SMP16[2:0] SMP15[2:1] Reserved SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] 15_0 Bits 31:24 Reserved, must be kept cleared. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel.
Page 235: Adc Sample Time Register 2 (Adc_Smpr2)
RM0008 Analog-to-digital converter (ADC) 11.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel.
Page 236: Adc Watchdog High Threshold Register (Adc_Htr)
Analog-to-digital converter (ADC) RM0008 11.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF Reserved HT[11:0] Reserved Bits 31:12 Reserved, must be kept cleared. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 11.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28...
Page 237: Adc Regular Sequence Register 1 (Adc_Sqr1)
RM0008 Analog-to-digital converter (ADC) 11.12.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 L[3:0] SQ16[4:1] Reserved SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] Bits 31:24 Reserved, must be kept cleared. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence.
Page 238: Adc Regular Sequence Register 2 (Adc_Sqr2)
Analog-to-digital converter (ADC) RM0008 11.12.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 SQ12[4:0] SQ11[4:0] SQ10[4:1] Reserved SQ10_ SQ9[4:0] SQ8[4:0] SQ7[4:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted.
Page 239: Adc Regular Sequence Register 3 (Adc_Sqr3)
RM0008 Analog-to-digital converter (ADC) 11.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 SQ6[4:0] SQ5[4:0] SQ4[4:1] Reserved SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept cleared. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted.
Page 240: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0008 11.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 JL[1:0] JSQ4[4:1] Reserved JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept cleared. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 241: Adc Regular Data Register (Adc_Dr)
RM0008 Analog-to-digital converter (ADC) Bits 31:16 Reserved, must be kept cleared. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 27 Figure 11.12.14 ADC regular data register (ADC_DR) Address offset: 0x4C...
Page 242 Analog-to-digital converter (ADC) RM0008 Table 72. ADC register map and reset values (continued) Offset Register ADC_JOFR1 JOFFSET1[11:0] 0x14 Reserved Reset value ADC_JOFR2 JOFFSET2[11:0] 0x18 Reserved Reset value ADC_JOFR3 JOFFSET3[11:0] 0x1C Reserved Reset value ADC_JOFR4 JOFFSET4[11:0] 0x20 Reserved Reset value ADC_HTR HT[11:0] 0x24 Reserved...
Page 243: Digital-To-Analog Converter (Dac)
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to connectivity line, high-density and XL-density STM32F101xx and STM32F103xx devices only. 12.1 DAC introduction The DAC module is a 12-bit, voltage output digital-to-analog converter.
Page 244: Table 73. Dac Pins
Digital-to-analog converter (DAC) RM0008 Figure 40. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 245: Dac Functional Description
RM0008 Digital-to-analog converter (DAC) 12.3 DAC functional description 12.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 246: Dac Conversion
Digital-to-analog converter (DAC) RM0008 Figure 41. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 ● Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) –...
Page 247: Dac Output Voltage
RM0008 Digital-to-analog converter (DAC) Figure 43. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 12.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation:...
Page 248: Dma Request
Digital-to-analog converter (DAC) RM0008 Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to- DAC_DORx register transfer. 12.3.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
Page 249: Triangle-Wave Generation
RM0008 Digital-to-analog converter (DAC) Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK 0x00 0xD55 0xAAA SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. 12.3.9 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
Page 250: Dual Dac Channel Conversion
Digital-to-analog converter (DAC) RM0008 Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
Page 251: Independent Trigger With Same Lfsr Generation
RM0008 Digital-to-analog converter (DAC) 12.4.2 Independent trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits ●...
Page 252: Independent Trigger With Different Triangle Generation
Digital-to-analog converter (DAC) RM0008 DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later).
Page 253: Simultaneous Trigger With Same Lfsr Generation
RM0008 Digital-to-analog converter (DAC) 12.4.8 Simultaneous trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: ● Set the two DAC channel trigger enable bits TEN1 and TEN2 ● Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits ●...
Page 254: Simultaneous Trigger With Different Triangle Generation
Digital-to-analog converter (DAC) RM0008 added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 12.4.11 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: ●...
Page 255 RM0008 Digital-to-analog converter (DAC) Bit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ Triangle Amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ Triangle Amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ Triangle Amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ Triangle Amplitude equal to 15...
Page 256 Digital-to-analog converter (DAC) RM0008 Bits 15:13 Reserved. Bit 12 DMAEN1: DAC channel1 DMA enable This bit is set and cleared by software. 0: DAC channel1 DMA mode disabled 1: DAC channel1 DMA mode enabled Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.
Page 257: Dac Software Trigger Register (Dac_Swtrigr)
RM0008 Digital-to-analog converter (DAC) Bit 1 BOFF1: DAC channel1 output buffer disable This bit set and cleared by software to enable/disable DAC channel1 output buffer. 0: DAC channel1 output buffer enabled 1: DAC channel1 output buffer disabled Bit 0 EN1: DAC channel1 enable This bit set and cleared by software to enable/disable DAC channel1.
Page 258: Dac Channel1 12-Bit Right-Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0008 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) Address offset: 0x08 Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:12 Reserved. Bit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
Page 259: Dac Channel2 12-Bit Right Aligned Data Holding Register
RM0008 Digital-to-analog converter (DAC) 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
Page 260: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
Digital-to-analog converter (DAC) RM0008 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 15:12 Reserved.
Page 261: Dual Dac 8-Bit Right Aligned Data Holding Register
RM0008 Digital-to-analog converter (DAC) 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel1.
Page 262: Dac Register Map
Digital-to-analog converter (DAC) RM0008 12.5.14 DAC register map The following table summarizes the DAC registers. Table 75. DAC register map Offset Register WAVE WAVE TSEL1 DAC_CR MAMP2[3:0] TSEL2[2:0] MAMP1[3:0] 2[2:0] 1[2:0] [2:0] 0x00 Reserved Reserved Reset value DAC_SWTRIG 0x04 Reserved Reset value DAC_DHR12R DACC1DHR[11:0]...
Page 263: Dma Controller (Dma)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 264: Figure 48. Dma Block Diagram In Connectivity Line Devices
DMA controller (DMA) RM0008 The block diagram is shown in Figure Figure 48. DMA block diagram in connectivity line devices 264/1096 Doc ID 13902 Rev 12...
Page 265: Dma Functional Description
RM0008 DMA controller (DMA) Figure 49. DMA block diagram in low-, medium- high- and XL-density devices ICode Flash FLITF DCode Cortex-M3 Sys tem SRAM DMA1 Ch.1 FSMC Ch.2 SDIO Bridge 2 AHB System Ch.7 APB2 Bridge 1 APB1 Arbiter USART1 TIM2 USART2 DMA request...
Page 266: Arbiter
DMA controller (DMA) RM0008 In summary, each DMA transfer consists of three operations: ● The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register ●...
Page 267 RM0008 DMA controller (DMA) addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled.
Page 268: Programmable Data Width, Data Alignment And Endians
DMA controller (DMA) RM0008 The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 13.3.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 76: Programmable data width &...
Page 269: Error Management
RM0008 DMA controller (DMA) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: ● To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord ●...
Page 270: Dma Request Mapping
DMA controller (DMA) RM0008 13.3.7 DMA request mapping DMA1 controller The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and USARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only one request must be enabled at a time. Refer to Figure 50: DMA1 request mapping.
Page 271: Table 78. Summary Of Dma1 Requests For Each Channel
RM0008 DMA controller (DMA) Table 78 lists the DMA requests for each channel. Table 78. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI2/I2S2_R SPI2/I2S2_T SPI/I SPI1_RX...
Page 272: Table 79. Summary Of Dma2 Requests For Each Channel
DMA controller (DMA) RM0008 Figure 51. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 HIGH PRIORITY TIM5_TRIG HW request 1 Channel 1 TIM8_CH3 TIM8_UP SW trigger (MEM2MEM bit) SPI/I2S3_RX Channel 1 EN bit TIM8_CH4 HW request 2 TIM8_TRIG Channel 2 TIM8_COM TIM5_CH3...
Page 273: Dma Registers
RM0008 DMA controller (DMA) 13.4 DMA registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. Note: In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels.
Page 274: Dma Interrupt Flag Clear Register (Dma
DMA controller (DMA) RM0008 13.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF7 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 Reserved CTEIF4 CHTIF4 CTCIF4 CGIF4 CTEIF3 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, always read as 0.
Page 275: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
RM0008 DMA controller (DMA) 13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Reserved MEM2 PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC TEIE HTIE...
Page 276: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
DMA controller (DMA) RM0008 Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable...
Page 277: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
RM0008 DMA controller (DMA) 13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7), where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address...
Page 278: Dma Register Map
DMA controller (DMA) RM0008 13.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 80. DMA register map and reset values Offset Register DMA_ISR 0x000 Reserved Reset value DMA_IFCR 0x004 Reserved Reset value DMA_CCR1 [1:0] 0x008...
Page 279 RM0008 DMA controller (DMA) Table 80. DMA register map and reset values (continued) Offset Register DMA_CPAR4 PA[31:0] 0x04C Reset value DMA_CMAR4 MA[31:0] 0x050 Reset value 0x054 Reserved DMA_CCR5 [1:0] 0x058 Reserved Reset value DMA_CNDTR5 NDT[15:0] 0x05C Reserved Reset value DMA_CPAR5 PA[31:0] 0x060 Reset value...
Page 280: Advanced-Control Timers (Tim1&Tim8)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 281: Tim1&Tim8 Main Features
RM0008 Advanced-control timers (TIM1&TIM8) 14.2 TIM1&TIM8 main features TIM1&TIM8 timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65535. ●...
Page 282: Figure 52. Advanced-Control Timer Block Diagram
Advanced-control timers (TIM1&TIM8) RM0008 Figure 52. Advanced-control timer block diagram Internal Clock (CK_INT) CK_TIM18 from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO Input Filter TIMx_ETR Detector & Prescaler to other timers ITR0 to DAC/ADC ITR1 Slave Reset, Enable, Up/Down, Count ITR2 Mode TRGI...
Page 283: Tim1&Tim8 Functional Description
RM0008 Advanced-control timers (TIM1&TIM8) 14.3 TIM1&TIM8 functional description 14.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 284: Counter Modes
Advanced-control timers (TIM1&TIM8) RM0008 Figure 53. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 54.
Page 285: Figure 55. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 Advanced-control timers (TIM1&TIM8) preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
Page 286: Figure 57. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1&TIM8) RM0008 Figure 57. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 58. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 287: Figure 60. Counter Timing Diagram, Update Event When Arpe=1
RM0008 Advanced-control timers (TIM1&TIM8) Figure 60. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR...
Page 288: Figure 61. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0008 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 61. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV)
Page 289: Figure 64. Counter Timing Diagram, Internal Clock Divided By N
RM0008 Advanced-control timers (TIM1&TIM8) Figure 64. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 65. Counter timing diagram, update event when repetition counter is not used CK_PSC Timer clock = CK_CNT...
Page 290: Figure 66. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1&TIM8) RM0008 The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 291: Figure 67. Counter Timing Diagram, Internal Clock Divided By 2
RM0008 Advanced-control timers (TIM1&TIM8) Figure 67. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT...
Page 292: Repetition Counter
Advanced-control timers (TIM1&TIM8) RM0008 Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 293: Figure 72. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0008 Advanced-control timers (TIM1&TIM8) The repetition counter is decremented: ● At each counter overflow in upcounting mode, ● At each counter underflow in downcounting mode, ● At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 294: Clock Selection
Advanced-control timers (TIM1&TIM8) RM0008 14.3.4 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin ● External clock mode2: external trigger input ETR ● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 295: Figure 75. Control Circuit In External Clock Mode 1
RM0008 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 296: Capture/Compare Channels
Advanced-control timers (TIM1&TIM8) RM0008 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 297: Figure 78. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0008 Advanced-control timers (TIM1&TIM8) Figure 78. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_Falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P (from slave mode TIMx_CCMR1 TIMx_CCER controller) TI2F_rising...
Page 298: Input Capture Mode
Advanced-control timers (TIM1&TIM8) RM0008 Figure 80. Output stage of capture/compare channel (channel 1 to 3) Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER OC1CE OC1M[2:0] DTG[7:0] CC1NE...
Page 299: Pwm Input Mode
RM0008 Advanced-control timers (TIM1&TIM8) The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: ● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register.
Page 300: Forced Output Mode
Advanced-control timers (TIM1&TIM8) RM0008 For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): ● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 301: Output Compare Mode
RM0008 Advanced-control timers (TIM1&TIM8) Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 14.3.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 302: Pwm Mode
Advanced-control timers (TIM1&TIM8) RM0008 Figure 83. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A B200 B201 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 14.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 303: Figure 84. Edge-Aligned Pwm Waveforms (Arr=8)
RM0008 Advanced-control timers (TIM1&TIM8) PWM edge-aligned mode ● Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 284. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 304: Figure 85. Center-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0008 Figure 85. Center-aligned PWM waveforms (ARR=8) Hints on using center-aligned mode: ● When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Page 305: Complementary Outputs And Dead-Time Insertion
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.11 Complementary outputs and dead-time insertion The advanced-control timers (TIM1&TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 306: Using The Break Function
Advanced-control timers (TIM1&TIM8) RM0008 Figure 88. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 14.4.18: TIM1&TIM8 break and dead- time register (TIMx_BDTR) on page 341 for delay calculation.
Page 307 RM0008 Advanced-control timers (TIM1&TIM8) must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): ● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit).
Page 308: Figure 89. Output Behavior In Response To A Break
Advanced-control timers (TIM1&TIM8) RM0008 Figure 89. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 309: Clearing The Ocxref Signal On An External Event
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 310: 6-Step Pwm Generation
Advanced-control timers (TIM1&TIM8) RM0008 14.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 311: One-Pulse Mode
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 312: Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0008 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ● The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 313: Table 81. Counting Direction Versus Encoder Signals
RM0008 Advanced-control timers (TIM1&TIM8) repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 314: Figure 93. Example Of Counter Operation In Encoder Interface Mode
Advanced-control timers (TIM1&TIM8) RM0008 Figure 93. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down Figure 94 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 94.
Page 315: Timer Input Xor Function
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 316: Figure 95. Example Of Hall Sensor Interface
Advanced-control timers (TIM1&TIM8) RM0008 written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). Figure 95 describes this example. Figure 95. Example of hall sensor interface TIH1 TIH2 TIH3...
Page 317: Timx And External Trigger Synchronization
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 318: Figure 97. Control Circuit In Gated Mode
Advanced-control timers (TIM1&TIM8) RM0008 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: ● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 319: Figure 98. Control Circuit In Trigger Mode
RM0008 Advanced-control timers (TIM1&TIM8) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 320: Timer Synchronization
Advanced-control timers (TIM1&TIM8) RM0008 Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source –...
Page 321: Tim1&Tim8 Registers
RM0008 Advanced-control timers (TIM1&TIM8) 14.4 TIM1&TIM8 registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0]...
Page 322: Tim1&Tim8 Control Register 2 (Timx_Cr2)
Advanced-control timers (TIM1&TIM8) RM0008 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 323 RM0008 Advanced-control timers (TIM1&TIM8) Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 324: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 325 RM0008 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 326: Tim1&Tim8 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1&TIM8) RM0008 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 327 RM0008 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
Page 328: Tim1&Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, always read as 0. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag...
Page 329: Tim1&Tim8 Event Generation Register (Timx_Egr)
RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 330 Advanced-control timers (TIM1&TIM8) RM0008 Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Page 331: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 332 Advanced-control timers (TIM1&TIM8) RM0008 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 333 RM0008 Advanced-control timers (TIM1&TIM8) Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 334: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0008 Bits 1:0 CC1S: Capture/Compare 1 Selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC.
Page 335: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 336 Advanced-control timers (TIM1&TIM8) RM0008 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high.
Page 337 RM0008 Advanced-control timers (TIM1&TIM8) Table 83. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not Output Disabled (not driven by driven by the timer) the timer) OCx=0, OCx_EN=0...
Page 338: Tim1&Tim8 Counter (Timx_Cnt)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 339: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, always read as 0. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 340: Tim1&Tim8 Capture/Compare Register 2 (Timx_Ccr2)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 341: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 342 Advanced-control timers (TIM1&TIM8) RM0008 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 343: Tim1&Tim8 Dma Control Register (Timx_Dcr)
RM0008 Advanced-control timers (TIM1&TIM8) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 344: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
Advanced-control timers (TIM1&TIM8) RM0008 Bits 4:0 DBA[4:0]: DMA base address This 5-bits vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2,...
Page 345 RM0008 Advanced-control timers (TIM1&TIM8) Table 84. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CR2 MMS[2:0] 0x04 Reserved Reset value ETPS TIMx_SMCR ETF[3:0] TS[2:0] SMS[2:0] [1:0] 0x08 Reserved Reset value TIMx_DIER 0x0C Reserved Reset value TIMx_SR 0x10 Reserved Reset value TIMx_EGR 0x14 Reserved...
Page 346 Advanced-control timers (TIM1&TIM8) RM0008 Table 84. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCR4 CCR4[15:0] 0x40 Reserved Reset value LOCK TIMx_BDTR DT[7:0] [1:0] 0x44 Reserved Reset value TIMx_DCR DBL[4:0] DBA[4:0] 0x48 Reserved Reserved Reset value TIMx_DMAR DMAB[15:0] 0x4C Reserved Reset value Refer to...
Page 347: General-Purpose Timers (Tim2 To Tim5)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 348: Timx Main Features
General-purpose timers (TIM2 to TIM5) RM0008 15.2 TIMx main features General-purpose TIMx timer features include: ● 16-bit up, down, up/down auto-reload counter. ● 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535. ●...
Page 349: Timx Functional Description
RM0008 General-purpose timers (TIM2 to TIM5) Figure 100. General-purpose timer block diagram Internal Clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity selection & edge TIMx_ETR Input filter detector & prescaler TRGO ITR0 Trigger to other timers controller ITR1 to DAC/ADC ITR2 TRGI Slave...
Page 350: Figure 101. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 to TIM5) RM0008 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 351: Counter Modes
RM0008 General-purpose timers (TIM2 to TIM5) Figure 102. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 15.3.2...
Page 352: Figure 103. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0008 Figure 103. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 104.
Page 353: Figure 106. Counter Timing Diagram, Internal Clock Divided By N
RM0008 General-purpose timers (TIM2 to TIM5) Figure 106. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 354: Figure 108. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2 to TIM5) RM0008 Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 355: Figure 109. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 General-purpose timers (TIM2 to TIM5) Figure 109. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 110.
Page 356: Figure 112. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0008 Figure 112. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 113. Counter timing diagram, Update event when repetition counter is not used CK_INT CNT_EN...
Page 357: Figure 114. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0008 General-purpose timers (TIM2 to TIM5) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 358: Figure 115. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0008 Figure 115. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TImer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 116.
Page 359: Figure 118. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow)
RM0008 General-purpose timers (TIM2 to TIM5) Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 360: Clock Selection
General-purpose timers (TIM2 to TIM5) RM0008 15.3.3 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (CK_INT) ● External clock mode1: external input pin (TIx) ● External clock mode2: external trigger input (ETR) ●...
Page 361: Figure 121. Ti2 External Clock Connection Example
RM0008 General-purpose timers (TIM2 to TIM5) Figure 121. TI2 external clock connection example TIMx_SMCR TS[2:0] TI2F TI1F encoder ITRx mode TI1F_ED external clock TRGI TI1FP1 mode 1 CK_PSC TI2F_Rising TI2FP2 Edge Filter Detector TI2F_Falling ETRF external clock ETRF mode 2 CK_INT ICF[3:0] CC2P...
Page 362: Figure 123. External Trigger Input Block
General-purpose timers (TIM2 to TIM5) RM0008 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 123 gives an overview of the external trigger input block.
Page 363: Capture/Compare Channels
RM0008 General-purpose timers (TIM2 to TIM5) 15.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel.
Page 364: Figure 127. Output Stage Of Capture/Compare Channel (Channel 1)
General-purpose timers (TIM2 to TIM5) RM0008 Figure 127. Output stage of capture/compare channel (channel 1) ETRF To the master mode controller Output Enable Circuit CC1P CNT > CCR1 oc1ref Output mode TIMx_CCER CNT = CCR1 controller CC1E TIMx_CCER OC1M[2:0] TIMx_CCMR1 The capture/compare block is made of one preload register and one shadow register.
Page 365: Input Capture Mode
RM0008 General-purpose timers (TIM2 to TIM5) 15.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 366: Pwm Input Mode
General-purpose timers (TIM2 to TIM5) RM0008 15.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: ● Two ICx signals are mapped on the same TIx input. ● These 2 ICx signals are active on edges with opposite polarity. ●...
Page 367: Forced Output Mode
RM0008 General-purpose timers (TIM2 to TIM5) 15.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
Page 368: Pwm Mode
General-purpose timers (TIM2 to TIM5) RM0008 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 129.
Page 369: Figure 130. Edge-Aligned Pwm Waveforms (Arr=8)
RM0008 General-purpose timers (TIM2 to TIM5) This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low.
Page 370: Figure 131. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0008 Figure 131 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR=8, ● PWM mode is the PWM mode 1, ● The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 371: One-Pulse Mode
RM0008 General-purpose timers (TIM2 to TIM5) – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. ● The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running.
Page 372: Clearing The Ocxref Signal On An External Event
General-purpose timers (TIM2 to TIM5) RM0008 The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ●...
Page 373: Encoder Interface Mode
RM0008 General-purpose timers (TIM2 to TIM5) Figure 133. Clearing TIMx OCxREF (CCRx) counter (CNT) ETRF OCxREF (OCxCE=0) OCxREF (OCxCE=1) OCREF_CLR OCREF_CLR becomes high still high 15.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Page 374: Table 85. Counting Direction Versus Encoder Signals
General-purpose timers (TIM2 to TIM5) RM0008 Table 85. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count...
Page 375: Timer Input Xor Function
RM0008 General-purpose timers (TIM2 to TIM5) Figure 135 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 135. Example of encoder interface mode with IC1FP1 polarity inverted. forward jitter backward jitter forward Counter down...
Page 376: Figure 136. Control Circuit In Reset Mode
General-purpose timers (TIM2 to TIM5) RM0008 prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). ●...
Page 377: Figure 137. Control Circuit In Gated Mode
RM0008 General-purpose timers (TIM2 to TIM5) Figure 137. Control circuit in gated mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 32 33 35 36 37 38 Write TIF=0 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: ●...
Page 378: Timer Synchronization
General-purpose timers (TIM2 to TIM5) RM0008 In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: –...
Page 379: Figure 140. Master/Slave Timer Example
RM0008 General-purpose timers (TIM2 to TIM5) Using one timer as prescaler for another Figure 140. Master/Slave timer example TIM1 TIM2 Clock Master Slave CK_PSC TRGO1 ITR1 mode mode control Counter Prescaler Counter Prescaler control Input trigger selection For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 140.
Page 380: Figure 141. Gating Timer 2 With Oc1Ref Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0008 Figure 141. Gating timer 2 with OC1REF of timer 1 CK_INT TIMER1-OC1REF TIMER1-CNT TIMER2-CNT 3045 3046 3047 3048 TIMER 2-TIF Write TIF=0 In the example in Figure 141, the Timer 2 counter and prescaler are not initialized before being started.
Page 381: Figure 142. Gating Timer 2 With Enable Of Timer 1
RM0008 General-purpose timers (TIM2 to TIM5) Figure 142. Gating timer 2 with Enable of timer 1 CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 write CNT TIMER 2-TIF Write TIF=0 Using one timer to start another timer In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to Figure 140 for connections.
Page 382: Figure 144. Triggering Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0008 As in the previous example, you can initialize both counters before starting counting. Figure 144 shows the behavior with the same configuration as in Figure 143 but in trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register). Figure 144.
Page 383: Debug Mode
RM0008 General-purpose timers (TIM2 to TIM5) counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer 2): ● Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the TIM1_CR2 register).
Page 384: Timx2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0008 15.4 TIMx2 to TIM5 registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 15.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000...
Page 385 RM0008 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 386: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 TI1S MMS[2:0] CCDS Reserved Reserved Bits 15:8 Reserved, always read as 0. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 14.3.18: Interfacing with Hall sensors on page 315...
Page 387: Timx Slave Mode Control Register (Timx_Smcr)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 388: Table 86. Timx Internal Trigger Connection
General-purpose timers (TIM2 to TIM5) RM0008 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.
Page 389 RM0008 General-purpose timers (TIM2 to TIM5) Table 86. TIMx Internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM4 TIM1 TIM2 TIM3 TIM8 TIM5 TIM2 TIM3 TIM4 TIM8 1.
Page 390: Timx Dma/Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC4DE CC3DE CC2DE CC1DE CC4IE CC3IE CC2IE CC1IE Res. Res. Bit 15 Reserved, always read as 0. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 391: Timx Status Register (Timx_Sr)
RM0008 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 392 General-purpose timers (TIM2 to TIM5) RM0008 Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 393: Timx Event Generation Register (Timx_Egr)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 CC4G CC3G CC2G CC1G Reserved Res. Bits 15:7 Reserved, always read as 0. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 394: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 395 RM0008 General-purpose timers (TIM2 to TIM5) Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 396 General-purpose timers (TIM2 to TIM5) RM0008 Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 397: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 398: Timx Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM2 to TIM5) RM0008 Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 399: Timx Counter (Timx_Cnt)
RM0008 General-purpose timers (TIM2 to TIM5) Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bits 3:2 Reserved, always read as 0. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low.
Page 400: Timx Auto-Reload Register (Timx_Arr)
General-purpose timers (TIM2 to TIM5) RM0008 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event. 15.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 401: Timx Capture/Compare Register 1 (Timx_Ccr1)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.13 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 402: Timx Capture/Compare Register 3 (Timx_Ccr3)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 CCR3[15:0] Bits 15:0 CCR3[15:0]: Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE).
Page 403: Timx Dma Control Register (Timx_Dcr)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 DBL[4:0] DBA[4:0] Reserved Reserved Bits 15:13 Reserved, always read as 0 Bits 12:8 DBL[4:0]: DMA burst length This 5-bits vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e.
Page 404 General-purpose timers (TIM2 to TIM5) RM0008 Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write access to the DMAR register accesses the register located at the address: “(TIMx_CR1 address) + DBA + (DMA index)” in which: TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in the TIMx_DCR register, DMA index is the offset automatically controlled by the DMA transfer, depending on the length of the transfer DBL in the TIMx_DCR register.
Page 405: Timx Register Map
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.19 TIMx register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 88. TIMx register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value MMS[2:0 TIMx_CR2 Reserve...
Page 406 General-purpose timers (TIM2 to TIM5) RM0008 (continued) Offset Register TIMx_PSC PSC[15:0] 0x28 Reserved Reset value TIMx_ARR ARR[15:0] 0x2C Reserved Reset value 0x30 Reserved TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reserved Reset value TIMx_CCR4 CCR4[15:0] 0x40...
Page 407 RM0008 General-purpose timers (TIM2 to TIM5) Doc ID 13902 Rev 12 407/1096...
Page 408: General-Purpose Timers (Tim9 To Tim14)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 409: Tim9 To Tim14 Main Features
RM0008 General-purpose timers (TIM9 to TIM14) 16.2 TIM9 to TIM14 main features 16.2.1 TIM9/TIM12 main features The features of the TIM9/TIM12 general-purpose timers include: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed “on the fly”) ●...
Page 410: Tim10/Tim11 And Tim13/Tim14 Main Features
General-purpose timers (TIM9 to TIM14) RM0008 16.3 TIM10/TIM11 and TIM13/TIM14 main features The features of general-purpose timers TIM10/TIM11 and TIM13/TIM14 include: ● 16-bit auto-reload upcounter ● 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed “on the fly”) ●...
Page 411: Tim9 To Tim14 Functional Description
RM0008 General-purpose timers (TIM9 to TIM14) 16.4 TIM9 to TIM14 functional description 16.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up. The counter clock can be divided by a prescaler.
Page 412: Counter Modes
General-purpose timers (TIM9 to TIM14) RM0008 Figure 148. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 149.
Page 413: Figure 150. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 General-purpose timers (TIM9 to TIM14) setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): ●...
Page 414: Figure 152. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM9 to TIM14) RM0008 Figure 152. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 153. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 415: Clock Selection
RM0008 General-purpose timers (TIM9 to TIM14) Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 416: Figure 156. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM9 to TIM14) RM0008 Figure 156. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1( TIM9 and TIM12) This mode is selected when SMS=’111’...
Page 417: Capture/Compare Channels
RM0008 General-purpose timers (TIM9 to TIM14) Figure 158. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 16.4.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 418: Input Capture Mode
General-purpose timers (TIM9 to TIM14) RM0008 Figure 160. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/compare preload register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/compare shadow register CC1S[0]...
Page 419: Pwm Input Mode (Only For Tim9/12)
RM0008 General-purpose timers (TIM9 to TIM14) cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 420: Forced Output Mode
General-purpose timers (TIM9 to TIM14) RM0008 Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
Page 421: Output Compare Mode
RM0008 General-purpose timers (TIM9 to TIM14) 16.4.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
Page 422: Pwm Mode
General-purpose timers (TIM9 to TIM14) RM0008 Figure 163. Output compare mode, toggle on OC1. Write B201h in the CC1R register TIM1_CNT 0039 003A B200 B201 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 16.4.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 423: Figure 164. Edge-Aligned Pwm Waveforms (Arr=8)
RM0008 General-purpose timers (TIM9 to TIM14) Figure 164. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF ‚Äò CCRx>8 CCxIF ‚Äò OCXREF CCRx=0 CCxIF Doc ID 13902 Rev 12 423/1096...
Page 424: One-Pulse Mode (Only For Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0008 16.4.10 One-pulse mode (only for TIM9/12) One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 425 RM0008 General-purpose timers (TIM9 to TIM14) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). ● The t is defined by the value written in the TIMx_CCR1 register. DELAY ●...
Page 426: Tim9/12 External Trigger Synchronization
General-purpose timers (TIM9 to TIM14) RM0008 16.4.11 TIM9/12 external trigger synchronization The TIM9/12 timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 427: Figure 167. Control Circuit In Gated Mode
RM0008 General-purpose timers (TIM9 to TIM14) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’).
Page 428: Timer Synchronization (Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0008 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=’0000’).
Page 429: Tim9 And Tim12 Registers
RM0008 General-purpose timers (TIM9 to TIM14) 16.5 TIM9 and TIM12 registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. 16.5.1 TIM9/12 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS Reserved reserved Bits 15:10 Reserved, always read as 0 Bits 9:8 CKD: Clock division...
Page 430: Tim9/12 Control Register 2 (Timx_Cr2)
General-purpose timers (TIM9 to TIM14) RM0008 16.5.2 TIM9/12 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, always read as 0. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in Master mode to slave timers for synchronization (TRGO).
Page 431: Tim9/12 Slave Mode Control Register (Timx_Smcr)
RM0008 General-purpose timers (TIM9 to TIM14) 16.5.3 TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 TS[2:0] SMS[2:0] Reserved Res. Bits 15:8 Reserved. Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO).
Page 432: Tim9/12 Interrupt Enable Register (Timx_Dier)
General-purpose timers (TIM9 to TIM14) RM0008 Table 89. TIMx internal trigger connection Slave TIM ITR0 (TS =’ 000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ’011’) TIM2 TIM1 TIM8 TIM3 TIM4 TIM3 TIM1 TIM2 TIM5 TIM4 TIM4 TIM1 TIM2...
Page 433: Tim9/12 Status Register (Timx_Sr)
RM0008 General-purpose timers (TIM9 to TIM14) 16.5.5 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC2OF CC1OF CC2IF CC1IF Reserved Reserved Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15:11 Reserved, always read as 0. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
Page 434: Tim9/12 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0008 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –At overflow and if UDIS=’0’...
Page 435: Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 General-purpose timers (TIM9 to TIM14) 16.5.7 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes.
Page 436 General-purpose timers (TIM9 to TIM14) RM0008 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
Page 437 RM0008 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 438: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM9 to TIM14) RM0008 16.5.8 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC2NP CC2P CC2E CC1NP CC1P CC1E Reserved Res. Res. Bits 15:8 Reserved, always read as 0. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, always read as 0.
Page 439: Tim9/12 Counter (Timx_Cnt)
RM0008 General-purpose timers (TIM9 to TIM14) Table 90. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 440: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0008 16.5.12 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 441: Tim9/12 Register Map
RM0008 General-purpose timers (TIM9 to TIM14) 16.5.14 TIM9/12 register map TIM9/12 registers are mapped as 16-bit addressable registers as described in the table below: Table 91. TIM9/12 register map and reset values Offset Register TIMx_CR1 0x00 Reserved [1:0] Reset value TIMx_CR2 MMS[2:0] 0x04...
Page 442: Tim10/11/13/14 Registers
General-purpose timers (TIM9 to TIM14) RM0008 16.6 TIM10/11/13/14 registers 16.6.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS Reserved Reserved Bits 15:10 Reserved, always read as 0. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 00: t CK_INT...
Page 443: Tim10/11/13/14 Interrupt Enable Register (Timx_Dier)
RM0008 General-purpose timers (TIM9 to TIM14) 16.6.2 TIM10/11/13/14 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC1IE Reserved Bits 15:2 Reserved, always read as 0. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled...
Page 444: Tim10/11/13/14 Event Generation Register (Timx_Egr)
General-purpose timers (TIM9 to TIM14) RM0008 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 445: Tim10/11/13/14 Capture/Compare Mode Register 1
RM0008 General-purpose timers (TIM9 to TIM14) 16.6.5 TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 446 General-purpose timers (TIM9 to TIM14) RM0008 Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON.
Page 447 RM0008 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:8 Reserved Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 448: Tim10/11/13/14 Capture/Compare Enable Register
General-purpose timers (TIM9 to TIM14) RM0008 16.6.6 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC1NP CC1P CC1E Reserved Res. Bits 15:4 Reserved, always read as 0. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared. CC1 channel configured as input: CC1NP bit is used in conjunction with CC1P to define TI1FP1 polarity (refer to CC1P description).
Page 449: Tim10/11/13/14 Counter (Timx_Cnt)
RM0008 General-purpose timers (TIM9 to TIM14) 16.6.7 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 16.6.8 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 450: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0008 16.6.10 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 451 RM0008 General-purpose timers (TIM9 to TIM14) Table 93. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_CNT CNT[15:0] 0x24 Reserved Reset value TIMx_PSC PSC[15:0] 0x28 Reserved Reset value TIMx_ARR ARR[15:0] 0x2C Reserved Reset value 0x30 Reserved TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value 0x38 to...
Page 452: Basic Timers (Tim6&Tim7)
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte. Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. This section applies to high-density and XL-density STM32F101xx and STM32F103xx devices, and to connectivity line devices only. 17.1 TIM6&TIM7 introduction...
Page 453: Tim6&Tim7 Functional Description
RM0008 Basic timers (TIM6&TIM7) Figure 169. Basic timer block diagram TRGO Trigger Internal clock (CK_INT) to DAC TIMxCLK from RCC controller Reset, Enable, Count, Controller Auto-reload Register Stop, Clear or up CK_PSC CK_CNT ± Prescaler COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt &...
Page 454: Figure 170. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6&TIM7) RM0008 Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.
Page 455: Counting Mode
RM0008 Basic timers (TIM6&TIM7) 17.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 456: Figure 173. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6&TIM7) RM0008 Figure 173. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 174. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT...
Page 457: Clock Source
RM0008 Basic timers (TIM6&TIM7) Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register...
Page 458: Debug Mode
Basic timers (TIM6&TIM7) RM0008 Figure 178. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 17.3.4 Debug mode When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP...
Page 459 RM0008 Basic timers (TIM6&TIM7) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
Page 460: Tim6&Tim7 Control Register 2 (Timx_Cr2)
Basic timers (TIM6&TIM7) RM0008 17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, always read as 0. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 461: Tim6&Tim7 Status Register (Timx_Sr)
RM0008 Basic timers (TIM6&TIM7) 17.4.4 TIM6&TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved rc_w0 Bits 15:1 Reserved, always read as 0. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 462: Tim6&Tim7 Prescaler (Timx_Psc)
Basic timers (TIM6&TIM7) RM0008 17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded into the active prescaler register at each update event. 17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 463: Tim6&Tim7 Register Map
RM0008 Basic timers (TIM6&TIM7) 17.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 94. TIM6&TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved Reset value 0x08...
Page 464: Real-Time Clock (Rtc)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 465: Rtc Main Features
RM0008 Real-time clock (RTC) 18.2 RTC main features ● Programmable prescaler: division factor up to 2 ● 32-bit programmable counter for long-term measurement ● Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) ●...
Page 466: Rtc Functional Description
Real-time clock (RTC) RM0008 18.3 RTC functional description 18.3.1 Overview The RTC consists of two main units (see Figure 179 on page 466). The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode (for more information refer to Section 18.4: RTC registers on page 469).
Page 467: Resetting Rtc Registers
RM0008 Real-time clock (RTC) 18.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset.
Page 468: Rtc Flag Assertion
Real-time clock (RTC) RM0008 18.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000.
Page 469: Rtc Registers
RM0008 Real-time clock (RTC) 18.4 RTC registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 18.4.1 RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 OWIE...
Page 470: Rtc Control Register Low (Rtc_Crl)
Real-time clock (RTC) RM0008 18.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 RTOFF ALRF SECF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not.
Page 471: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)
RM0008 Real-time clock (RTC) The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page 467).
Page 472: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)
Real-time clock (RTC) RM0008 RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 18.3.4 on page 467) Reset value: 0x8000 PRL[15:0] Bits 15:0 PRL[15:0]: RTC prescaler reload value low These bits are used to define the counter clock frequency according to the following formula: /(PRL[19:0]+1) TR_CLK RTCCLK...
Page 473: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)
RM0008 Real-time clock (RTC) 18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 474: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)
Real-time clock (RTC) RM0008 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 475: Rtc Register Map
RM0008 Real-time clock (RTC) 18.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 95. register map and reset values Offset Register RTC_CRH 0x00 Reserved Reset value RTC_CRL 0x04 Reserved Reset value RTC_PRLH PRL[19:16] 0x08...
Page 476: Independent Watchdog (Iwdg)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 477: Hardware Watchdog
RM0008 Independent watchdog (IWDG) Whenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. 19.3.1 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count.
Page 478: Register Access Protection
Independent watchdog (IWDG) RM0008 19.3.2 Register access protection Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you must first write the code 0x5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0xAAAA).
Page 479: Iwdg Registers
RM0008 Independent watchdog (IWDG) 19.4 IWDG registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 19.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 KEY[15:0]...
Page 480: Reload Register (Iwdg_Rlr)
Independent watchdog (IWDG) RM0008 19.4.3 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RL[11:0] Reserved rw rw rw...
Page 481: Iwdg Register Map
RM0008 Independent watchdog (IWDG) 19.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 97. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] 0x00 Reserved Reset value IWDG_PR PR[2:0] 0x04 Reserved Reset value IWDG_RLR RL[11:0] 0x08...
Page 482: Window Watchdog (Wwdg)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 483: Figure 183. Watchdog Block Diagram
RM0008 Window watchdog (WWDG) Figure 183. Watchdog block diagram Watchdog configuration register (WWDG_CFR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR Watchdog control register (WWDG_CR) WDGA 6-bit downcounter (CNT) PCLK1 (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.
Page 484: How To Program The Watchdog Timeout
Window watchdog (WWDG) RM0008 20.4 How to program the watchdog timeout You can use the formula in Figure 184 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 184.
Page 485: Wwdg Registers
RM0008 Window watchdog (WWDG) 20.6 WWDG registers Refer to Section 2.1 on page 46 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 20.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x7F Reserved WDGA...
Page 486: Configuration Register (Wwdg_Cfr)
Window watchdog (WWDG) RM0008 20.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x7F Reserved WDGTB[1:0] W[6:0] Reserved Bit 31:10 Reserved Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is only cleared by hardware after a reset.
Page 487: Wwdg Register Map
RM0008 Window watchdog (WWDG) 20.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 98. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reserved Reset value WWDG_CFR W[6:0] 0x04 Reserved Reset value WWDG_SR 0x08 Reserved...
Page 488: Flexible Static Memory Controller (Fsmc)
Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 489: Block Diagram
RM0008 Flexible static memory controller (FSMC) ● Write enable and byte lane select outputs for use with PSRAM and SRAM devices ● Translation of 32-bit wide AHB transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices ●...
Page 490: Ahb Interface
Flexible static memory controller (FSMC) RM0008 Figure 185. FSMC block diagram FSMC interrupt to NVIC FSMC_NE[4:1] NOR/PSRAM FSMC_NL (or NADV) signals FSMC_NBL[1:0] From clock FSMC_CLK controller memory HCLK controller FSMC_A[25:0] FSMC_D[15:0] Shared FSMC_NOE signals Configuration FSMC_NWE FSMC_NWAIT Registers FSMC_NCE[3:2] NAND signals FSMC_INT[3:2] NAND/PC Card...
Page 491: Supported Memories And Transactions
RM0008 Flexible static memory controller (FSMC) The effect of this AHB error depends on the AHB master which has attempted the R/W access: ● If it is the Cortex™-M3 CPU, a hard fault inetrrupt is generated ● If is is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.
Page 492: External Device Address Mapping
Flexible static memory controller (FSMC) RM0008 21.4 External device address mapping From the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256 Mbytes each (Refer to Figure 186): ● Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM regions with 4 dedicated Chip Select.
Page 493: Nand/Pc Card Address Mapping
RM0008 Flexible static memory controller (FSMC) HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table. Table 100.
Page 494: Nor Flash/Psram Controller
Flexible static memory controller (FSMC) RM0008 The application software uses the 3 sections to access the NAND Flash memory: ● To send a command to NAND Flash memory: the software must write the command value to any memory location in the command section. ●...
Page 495: External Memory Interface Signals
RM0008 Flexible static memory controller (FSMC) Table 103. Programmable NOR/PSRAM access parameters (continued) Parameter Function Access mode Unit Min. Max. Duration of the bus Asynchronous and AHB clock cycle Bust turn turnaround phase synchronous read (HCLK) Number of AHB clock cycles Clock divide AHB clock cycle (HCLK) to build one memory...
Page 496: Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0008 Table 105. Muxed I/O NOR Flash (continued) FSMC signal name Function Write enable Latch enable (this signal is called address valid, NADV, by some NOR NL(=NADV) Flash devices) NWAIT NOR Flash wait input signal to the FSMC NOR-Flash memories are addressed in 16-bit words.
Page 497 RM0008 Flexible static memory controller (FSMC) Table 107. NOR Flash/PSRAM supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Asynchronous Asynchronous Split into 2 FSMC Asynchronous NOR Flash accesses (muxed I/Os Split into 2 FSMC and nonmuxed Asynchronous accesses...
Page 498: General Timing Rules
Flexible static memory controller (FSMC) RM0008 21.5.3 General timing rules Signals synchronization ● All controller output signals change on the rising edge of the internal clock (HCLK) ● In synchronous write mode (PSRAM devices), the output data changes on the falling edge of the memory clock (CLK) 498/1096 Doc ID 13902 Rev 12...
Page 499: Nor Flash/Psram Controller Asynchronous Transactions
RM0008 Flexible static memory controller (FSMC) 21.5.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, SRAM) ● Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory ● The FSMC always samples the data before de-asserting the chip select signal NE. This guarantees that the memory data-hold timing constraint is met (chip enable high to data transition, usually 0 ns min.) ●...
Page 500: Figure 188. Mode1 Write Accesses
Flexible static memory controller (FSMC) RM0008 Figure 188. Mode1 write accesses Memory transaction A[25:0] NBL[1:0] 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14721c The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge.
Page 501: Table 109. Fsmc_Btrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 109. FSMC_BTRx bit fields Bit name Value to set number 31-16 0x0000 Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for read accesses). 15-8 DATAST This value cannot be 0 (minimum is 1). ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) .
Page 502: Table 110. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Figure 190. ModeA write accesses Memory transaction A[25:0] NBL[1:0] 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14721c The differences compared with mode1 are the toggling of NOE and the independent read and write timings.
Page 503: Table 111. Fsmc_Btrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 111. FSMC_BTRx bit fields Bit name Value to set number 31-30 29-28 ACCMOD 27-16 0x000 Duration of the second access phase (DATAST+3 HCLK cycles) in 15-8 DATAST read. This value cannot be 0 (minimum is 1) ADDSET Duration of the first access phase (ADDSET+1 HCLK cycles) in read.
Page 504: Figure 191. Mode2/B Read Accesses
Flexible static memory controller (FSMC) RM0008 Mode 2/B - NOR Flash Figure 191. Mode2/B read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles Data sampled Data strobe ai14724c Figure 192.
Page 505: Figure 193. Modeb Write Accesses
RM0008 Flexible static memory controller (FSMC) Figure 193. ModeB write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai15110b The differences with mode1 are the toggling of NADV and the independent read and write timings when extended mode is set (Mode B).
Page 506: Table 114. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 114. FSMC_BTRx bit fields Bit number Bit name Value to set 31-30 29-28 ACCMOD 0x1 if extended mode is set 27-16 0x000 Duration of the access second phase (DATAST+3 HCLK cycles) in 15-8 DATAST read.
Page 507: Figure 194. Modec Read Accesses
RM0008 Flexible static memory controller (FSMC) Mode C - NOR Flash - OE toggling Figure 194. ModeC read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK cycles HCLK cycles HCLK cycles Data sampled Data strobe ai14725c...
Page 508: Table 116. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 116. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-16 0x0000 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1 BURSTEN FACCEN MWID...
Page 509: Figure 196. Moded Read Accesses
RM0008 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 196. ModeD read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles (ADDHLD + 1) HCLK cycles...
Page 510: Table 119. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 119. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-16 0x0000 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1 BURSTEN FACCEN Set according to memory support...
Page 511: Figure 197. Muxed Read Accesses
RM0008 Flexible static memory controller (FSMC) Mode muxed - asynchronous access muxed NOR Flash Figure 197. Muxed read accesses Memory transaction A[25:16] NADV High data driven AD[15:0] Lower address by memory 1HCLK cycle (ADDSET +1) (DATAST + 1) 2 HCLK (BUSTURN + 1) cycles HCLK cycles...
Page 512: Table 123. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 122. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-16 0x0000 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. EXTMOD 13-10 WAITPOL Meaningful only if bit 15 is 1 BURSTEN FACCEN MWID...
Page 513: Figure 199. Asynchronous Wait During A Read Access
RM0008 Flexible static memory controller (FSMC) Memory asserts the WAIT signal aligned to NOE/NWE which toggles: data_setup phase >= 4 * HCLK + max_wait_assertion_time Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling) : if max_wait_assertion_time > (address_phase + hold_phase) data_setup phase >= 4 * HCLK + (max_wait_assertion_time - address_phase - hold_phase) otherwise...
Page 514: Figure 200. Asynchronous Wait During A Write Access
Flexible static memory controller (FSMC) RM0008 Figure 200. Asynchronous wait during a write access Memory transaction A[25:0] address phase data phase NWAIT don’t care 1HCLK D[15:0] data driven by FSMC 3HCLK ai15797 514/1096 Doc ID 13902 Rev 12...
Page 515: Synchronous Burst Transactions
RM0008 Flexible static memory controller (FSMC) 21.5.5 Synchronous burst transactions The memory clock, CLK, is a submultiple of HCLK according to the value of parameter CLKDIV. NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion).
Page 516: Figure 201. Wait Configurations
Flexible static memory controller (FSMC) RM0008 During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. There are two timing configurations for the NOR Flash NWAIT signal in burst mode: ●...
Page 517: Table 124. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) 1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 124.
Page 518: Table 125. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 124. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set BURSTEN FWPRLVL Set to protect memory from accidental write access FACCEN Set according to memory support MWID As needed MTYP 0x1 or 0x2 MUXEN As needed MBKEN...
Page 519: Figure 203. Synchronous Multiplexed Write Mode - Psram (Cram)
RM0008 Flexible static memory controller (FSMC) Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM) Memory transaction = burst of 2 half words HCLK A[25:16] addr[25:16] Hi-Z NADV NWAIT (WAITCFG = 0) (DATALAT + 2) inserted wait state CLK cycles A/D[15:0] Addr[15:0] data...
Page 520: Table 126. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 126. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 0x0000 CBURSTRW 18-15 EXTMOD When high, the first data after latency period is taken as always WAITEN valid, regardless of the wait from memory value WREN no effect on synchronous read WAITCFG...
Page 521: Nor/Psram Controller Registers
RM0008 Flexible static memory controller (FSMC) 21.5.6 NOR/PSRAM controller registers The peripheral registers have to be accessed by words (32-bit). SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DX This register contains the control information of each memory bank, used for SRAMs, ROMs and asynchronous or burst NOR Flash memories.
Page 522 Flexible static memory controller (FSMC) RM0008 Bit 11 WAITCFG: Wait timing configuration. For memory access in burst mode, the NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state: 0: NWAIT signal is active one data cycle before wait state (default after reset), 1: NWAIT signal is active during wait state (not for Cellular RAM).
Page 523 RM0008 Flexible static memory controller (FSMC) SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories.
Page 524 Flexible static memory controller (FSMC) RM0008 Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 187 Figure 198), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 ×...
Page 525 RM0008 Flexible static memory controller (FSMC) SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, ROMs and NOR Flash memories.
Page 526: Nand Flash/Pc Card Controller
Flexible static memory controller (FSMC) RM0008 Bits 7:4 ADDHLD: Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 196 Figure 198), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses: 0000: Reserved 0001: ADDHLD phase duration = 2 ×...
Page 527: External Memory Interface Signals
RM0008 Flexible static memory controller (FSMC) Table 128. Programmable NAND/PC Card access parameters Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) Memory setup AHB clock cycle to set up the address before the Read/Write time (HCLK) command assertion Minimum duration (HCLK clock AHB clock cycle...
Page 528 Flexible static memory controller (FSMC) RM0008 16-bit NAND Flash Table 130. 16-bit NAND Flash FSMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus NCE[x] Chip select, x = 2, 3 NOE(= NRE)
Page 529: Nand Flash / Pc Card Supported Memories And Transactions
RM0008 Flexible static memory controller (FSMC) 21.6.2 NAND Flash / PC Card supported memories and transactions Table 132 below shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear in gray.
Page 530: Nand Flash Operations
Flexible static memory controller (FSMC) RM0008 Figure 204. NAND/PC Card controller timing for common memory access HCLK Address NCEx High NREG, NIOW, NIOR MEMxSET + 1 MEMxWAIT + 1 MEMxHOLD + 1 NWE, MEMxHIZ write_data read_data Valid ai14732d 1. NOE remains high (inactive) during write access. NWE remains high (inactive) during read access. 2.
Page 531: Nand Flash Pre-Wait Functionality
RM0008 Flexible static memory controller (FSMC) the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FSMC, which can be used to implement the prewait functionality needed by some NAND Flash memories (see details in Section 21.6.5: NAND Flash pre-wait functionality on page 531).
Page 532: Error Correction Code Computation Ecc (Nand Flash)
Flexible static memory controller (FSMC) RM0008 When this functionality is needed, it can be guaranteed by programming the MEMHOLD value to meet the t timing, however any CPU read or write access to the NAND Flash then has the hold delay of (MEMHOLD + 1) HCLK cycles inserted from the rising edge of the NWE signal to the next access.
Page 533: Table 133. 16-Bit Pc-Card Signals And Access Type
RM0008 Flexible static memory controller (FSMC) the odd byte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on D7-0 if A0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low. The memory space is selected by asserting low nOE for read accesses or nWE for write accesses, combined with the low assertion of nCE2/nCE1 and nREG.
Page 534 Flexible static memory controller (FSMC) RM0008 Table 133. 16-bit PC-Card signals and access type (continued) Allowed/not Space Access Type Allowed Read Even Byte on D7-0 Not supported Read Odd Byte on D7-0 Not supported Write Even Byte on D7-0 Not supported Write Odd Byte on D7-0 Not supported I/O space...
Page 535: Nand Flash/Pc Card Controller Registers
RM0008 Flexible static memory controller (FSMC) 21.6.8 NAND Flash/PC Card controller registers The peripheral registers have to be accessed by words (32-bit). PC Card/NAND Flash control registers 2..4 (FSMC_PCR2..4) Address offset: 0xA0000000 + 0x40 + 0x20 * (x – 1), x = 2..4 Reset value: 0x0000 0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ECCPS...
Page 536 Flexible static memory controller (FSMC) RM0008 Bit 2 PBKEN: PC Card/NAND Flash memory bank enable bit. Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB 0: Corresponding memory bank is disabled (default after reset) 1: Corresponding memory bank is enabled Bit 1 PWAITEN: Wait feature enable bit.
Page 537 RM0008 Flexible static memory controller (FSMC) Bit 2 IFS: Interrupt falling edge status The flag is set by hardware and reset by software. 0: No interrupt falling edge occurred 1: Interrupt falling edge occurred Bit 1 ILS: Interrupt high-level status The flag is set by hardware and reset by software.
Page 538 Flexible static memory controller (FSMC) RM0008 Bits 7:0 MEMSETx: Common memory x setup time Defines the number of HCLK (+1 for PC Card, +2 for NAND) clock cycles to set up the address before the command assertion (NWE, NOE), for PC Card/NAND Flash read or write access to common memory space on socket x: 0000 0000: 1 HCLK cycle (for PC Card) / HCLK cycles (for NAND Flash) 1111 1111: 256 HCLK cycles (for PC Card) / 257 HCLK cycles (for NAND Flash) - (default...
Page 539 RM0008 Flexible static memory controller (FSMC) Bits 7:0 ATTSETx: Attribute memory x setup time Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for PC CARD/NAND Flash read or write access to attribute memory space on socket x: 0000 0000: 1 HCLK cycle 1111 1111: 256 HCLK cycles (default value after reset)
Page 540: Table 134. Ecc Result Relevant Bits
Flexible static memory controller (FSMC) RM0008 ECC result registers 2/3 (FSMC_ECCR2/3) Address offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3 Reset value: 0x0000 0000 These registers contain the current error correction code value computed by the ECC computation modules of the FSMC controller (one module per NAND Flash memory bank).
Page 541: Fsmc Register Map
RM0008 Flexible static memory controller (FSMC) 21.6.9 FSMC register map The following table summarizes the FSMC registers. Table 135. FSMC register map Offset Register FSMC_BCR1 Reserved Reserved 0xA000 0000 Reset value 0xA000 FSMC_BCR2 Reserved Reserved 0008 0xA000 FSMC_BCR3 Reserved Reserved 0010 0xA000 FSMC_BCR4...
Page 542 Flexible static memory controller (FSMC) RM0008 Table 135. FSMC register map (continued) Offset Register 0xA000 FSMC_PMEM4 MEMHIZx MEMHOLDx MEMWAITx MEMSETx 00A8 0xA000 FSMC_PATT2 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 006C 0xA000 FSMC_PATT3 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 008C 0xA000 FSMC_PATT4 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 00AC 0xA000...
Page 543: Secure Digital Input/Output Interface (Sdio)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 544: Sdio Bus Topology
Secure digital input/output interface (SDIO) RM0008 interface using a protocol that utilizes the existing MMC access primitives. The interface electrical and signaling definition is as defined in the MMC reference. The MultiMediaCard/SD bus connects cards to the controller. The current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.
Page 545: Figure 208. Sdio (Multiple) Block Write Operation
RM0008 Secure digital input/output interface (SDIO) Figure 208. SDIO (multiple) block write operation From host to card From card to host Stop command stops data transfer Data from host to card Command Response Command Response SDIO_CMD SDIO_D Busy Data block crc Data block crc Busy Busy...
Page 546: Sdio Functional Description
Secure digital input/output interface (SDIO) RM0008 22.3 SDIO functional description The SDIO consists of two parts: ● The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. ●...
Page 547: Sdio Adapter
RM0008 Secure digital input/output interface (SDIO) Table 136. SDIO I/O definitions Direction Description MultiMediaCard/SD/SDIO card clock. This pin is the clock from SDIO_CK Output host to card. MultiMediaCard/SD/SDIO card command. This pin is the SDIO_CMD Bidirectional bidirectional command/response signal. MultiMediaCard/SD/SDIO card data. These pins are the SDIO_D[7:0] Bidirectional bidirectional databus.
Page 548: Figure 213. Control Unit
Secure digital input/output interface (SDIO) RM0008 Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: ● power-off ● power-up ● power-on Figure 213. Control unit Control unit Power management Clock...
Page 549: Figure 214. Sdio Adapter Command Path
RM0008 Secure digital input/output interface (SDIO) Figure 214. SDIO adapter command path Status Control Command To control unit flag logic timer Adapter registers SDIO_CMDin Argument SDIO_CMDout Shift register To AHB interface Response registers ai14805 ● Command path state machine (CPSM) –...
Page 550: Figure 215. Command Path State Machine (Cpsm)
Secure digital input/output interface (SDIO) RM0008 Figure 215. Command path state machine (CPSM) CE-ATA Command On reset Completion signal Wait_CPL received or CPSM disabled or Command CRC failed CPSM Enabled and Idle Response received or Response Received in CE-ATA pending command disabled or command mode and no interrupt and CRC failed...
Page 551: Table 137. Command Format
RM0008 Secure digital input/output interface (SDIO) Figure 216. SDIO command transfer at least 8 SDIO_CK cycles Command Response Command SDIO_CK State Idle Send Wait Receive Idle Send SDIO_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives ai14707 ● Command format –...
Page 552: Table 138. Short Response Format
Secure digital input/output interface (SDIO) RM0008 Table 138. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 139. Long response format Bit position Width Value Description Start bit Transmission bit [133:128]...
Page 553: Figure 217. Data Path
RM0008 Secure digital input/output interface (SDIO) Data path The data path subunit transfers data to and from cards. Figure 217 shows a block diagram of the data path. Figure 217. Data path Data path Status Control Data To control unit flag logic timer...
Page 554: Figure 218. Data Path State Machine (Dpsm)
Secure digital input/output interface (SDIO) RM0008 Figure 218. Data path state machine (DPSM) On reset DPSM disabled DPSM enabled and Read Wait Read Wait Started and SD I/O mode enabled Disabled or FIFO underrun or Idle end of data or CRC fail Disabled or CRC fail or timeout Enable and not send...
Page 555: Table 141. Data Token Format
RM0008 Secure digital input/output interface (SDIO) Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host.
Page 556: Table 142. Transmit Fifo Status Flags
Secure digital input/output interface (SDIO) RM0008 Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive: – The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted –...
Page 557: Sdio Ahb Interface
RM0008 Secure digital input/output interface (SDIO) Table 143. Receive FIFO status flags Flag Description RXFIFOF Set to high when all 32 receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. Set to high when 8 or more receive FIFO words contain valid data.
Page 558: Card Functional Description
Secure digital input/output interface (SDIO) RM0008 Send CMD24 (WRITE_BLOCK) as follows: Program the SDIO data length register (SDIO data timer register should be already programmed before the card identification process) Program the SDIO argument register with the address location of the card where data is to be transferred Program the SDIO command register: CmdIndex with 24 (WRITE_BLOCK);...
Page 559: Card Identification Process
RM0008 Secure digital input/output interface (SDIO) By using these commands without including the voltage range as the operand, the SDIO card host can query each card and determine the common voltage range before placing out- of-range cards in the inactive state. This query is used when the SDIO card host is able to select a common voltage range or when the user requires notification that cards are not usable.
Page 560: Block Write
Secure digital input/output interface (SDIO) RM0008 The bus is activated. The SDIO card host sends IO_SEND_OP_COND (CMD5). The cards respond with the contents of their operation condition registers. The incompatible cards are set to the inactive state. The SDIO card host issues SET_RELATIVE_ADDR (CMD3) to an active card with an address.
Page 561: Stream Access, Stream Write And Stream Read (Multimediacard Only)
RM0008 Secure digital input/output interface (SDIO) The host can abort reading at any time, within a multiple block operation, regardless of its type. Transaction abort is done by sending the stop transmission command. If the card detects an error (for example, out of range, address misalignment or internal error) during a multiple block read operation (both types) it stops the data transmission and remains in the data state.
Page 562: Erase: Group Erase And Sector Erase
Secure digital input/output interface (SDIO) RM0008 Stream read (MultiMediaCard only) READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer. This command instructs the card to send its data, starting at a specified address, until the SDIO card host sends STOP_TRANSMISSION (CMD12). The stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command.
Page 563: Wide Bus Selection Or Deselection
RM0008 Secure digital input/output interface (SDIO) The card indicates that an erase is in progress by holding SDIO_D low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. 22.4.9 Wide bus selection or deselection Wide bus (4-bit bus width) operation mode is selected or deselected using SET_BUS_WIDTH (ACMD6).
Page 564 Secure digital input/output interface (SDIO) RM0008 the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required information for the command (the password setting mode, the PWD itself, and card lock/unlock).
Page 565 RM0008 Secure digital input/output interface (SDIO) Resetting the password Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes in the currently used password.
Page 566: Card Status Register
Secure digital input/output interface (SDIO) RM0008 The unlocking function is only valid for the current power session. When the PWD field is not clear, the card is locked automatically on the next power-up. An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Page 567: Table 144. Card Status
RM0008 Secure digital input/output interface (SDIO) Table 144. Card status Clear Bits Identifier Type Value Description condition The command address argument was out of the allowed range for this card. ’0’= no error ADDRESS_ A multiple block or stream read/write E R X OUT_OF_RANGE ’1’= error...
Page 568 Secure digital input/output interface (SDIO) RM0008 Table 144. Card status (continued) Clear Bits Identifier Type Value Description condition (Undefined by the standard) A generic ’0’= no error card error related to the (and detected ERROR ’1’= error during) execution of the last host command (e.g.
Page 569: Sd Status Register
RM0008 Secure digital input/output interface (SDIO) Table 144. Card status (continued) Clear Bits Identifier Type Value Description condition ’0’= no error Error in the sequence of the AKE_SEQ_ERROR ’1’= error authentication process Reserved for application specific commands Reserved for manufacturer test mode 22.4.12 SD status register The SD status contains status bits that are related to the SD memory card proprietary...
Page 570 Secure digital input/output interface (SDIO) RM0008 Table 145. SD status (continued) Clear Bits Identifier Type Value Description condition In the future, the 8 LSBs will ’00xxh’= SD Memory Cards as be used to define different defined in Physical Spec Ver1.01- variations of an SD memory 2.00 (’x’= don’t care).
Page 571: Table 146. Speed Class Code Field
RM0008 Secure digital input/output interface (SDIO) Table 146. Speed class code field SPEED_CLASS Value definition Class 0 Class 2 Class 4 Class 6 04h – FFh Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps.
Page 572: Table 148. Au_Size Field
Secure digital input/output interface (SDIO) RM0008 Table 148. AU_SIZE field (continued) AU_SIZE Value definition 4 MB Ah – Fh Reserved The maximum AU size, which depends on the card capacity, is defined in Table 149. The card can be set to any AU size between RU size and maximum AU size. Table 149.
Page 573: Sd I/O Mode
RM0008 Secure digital input/output interface (SDIO) Table 151. Erase timeout field (continued) ERASE_TIMEOUT Value definition --------- --------- 63 [sec] ERASE_OFFSET This 2-bit field indicates T and one of four values can be selected. This field is OFFSET meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 152.
Page 574: Commands And Responses
Secure digital input/output interface (SDIO) RM0008 suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following steps: Determines the function currently using the SDIO_D [3:0] line(s) Requests the lower-priority or slower transaction to suspend Waits for the transaction suspension to complete Begins the higher-priority transaction Waits for the completion of the higher priority transaction Restores the suspended transaction...
Page 575: Table 153. Block-Oriented Write Commands
RM0008 Secure digital input/output interface (SDIO) The bus transaction for a GEN_CMD is the same as the single-block read or write commands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning.
Page 576: Table 154. Block-Oriented Write Protection Commands
Secure digital input/output interface (SDIO) RM0008 Table 154. Block-oriented write protection commands Response Type Argument Abbreviation Description index format If the card has write protection features, this command sets the write protection bit [31:0] data CMD28 ac of the addressed group. The properties of SET_WRITE_PROT address write protection are coded in the card-...
Page 577: Response Formats
RM0008 Secure digital input/output interface (SDIO) Table 156. I/O mode commands (continued) Response Type Argument Abbreviation Description index format CMD40 bcr [31:0] stuff bits GO_IRQ_STATE Places the system in the interrupt mode. CMD41 Reserved Table 157. Lock card Response Type Argument Abbreviation Description...
Page 578: R1 (Normal Response Command)
Secure digital input/output interface (SDIO) RM0008 22.5.1 R1 (normal response command) Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits.
Page 579: R4 (Fast I/O)
RM0008 Secure digital input/output interface (SDIO) Table 161. R3 response Bit position Width (bits Value Description Start bit Transmission bit [45:40] ‘111111’ Reserved [39:8] OCR register [7:1] ‘1111111’ Reserved End bit 22.5.5 R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content.
Page 580: R5 (Interrupt Request)
Secure digital input/output interface (SDIO) RM0008 Table 163. R4b response (continued) Bit position Width (bits Value Description [7:1] Reserved End bit Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card.
Page 581: Sdio I/O Card-Specific Operations
RM0008 Secure digital input/output interface (SDIO) Table 165. R6 response (continued) Bit position Width (bits) Value Description [31:16] RCA [31:16] of winning card or of the host [39:8] Argument field [15:0] Not defined. May be used for IRQ data [7:1] CRC7 End bit The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card.
Page 582: Sdio Suspend/Resume Operation
Secure digital input/output interface (SDIO) RM0008 As SDIO_CK is stopped, any command can be issued to the card. During a read/wait interval, the SDIO can detect SDIO interrupts on SDIO_D1. 22.6.3 SDIO suspend/resume operation While sending data to the card, the SDIO can suspend the write operation. the SDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command.
Page 583: Ce-Ata Interrupt
RM0008 Secure digital input/output interface (SDIO) When ‘0’ is received on the CMD line, the CPSM enters the Idle state. No new command can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven to ‘1’...
Page 584: Sdio Power Control Register (Sdio_Power)
Secure digital input/output interface (SDIO) RM0008 22.9.1 SDIO power control register (SDIO_POWER) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PWRC Reserved rw rw...
Page 585: Sdio Argument Register (Sdio_Arg)
RM0008 Secure digital input/output interface (SDIO) Bit 10 BYPASS: Clock divider bypass enable bit 0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal. 1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal. Bit 9 PWRSAV: Power saving configuration bit For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting PWRSAV:...
Page 586: Sdio Command Register (Sdio_Cmd)
Secure digital input/output interface (SDIO) RM0008 22.9.4 SDIO command register (SDIO_CMD) Address offset: 0x0C Reset value: 0x0000 0000 The SDIO_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
Page 587: Sdio Command Response Register (Sdio_Respcmd)
RM0008 Secure digital input/output interface (SDIO) argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. CE-ATA devices send only short responses. 22.9.5 SDIO command response register (SDIO_RESPCMD) Address offset: 0x10 Reset value: 0x0000 0000 The SDIO_RESPCMD register contains the command index field of the last command...
Page 588: Sdio Data Timer Register (Sdio_Dtimer)
Secure digital input/output interface (SDIO) RM0008 22.9.7 SDIO data timer register (SDIO_DTIMER) Address offset: 0x24 Reset value: 0x0000 0000 The SDIO_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDIO_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state.
Page 589: Sdio Data Control Register (Sdio_Dctrl)
RM0008 Secure digital input/output interface (SDIO) 22.9.9 SDIO data control register (SDIO_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDIO_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DBLOCKSIZE Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 590: Sdio Data Counter Register (Sdio_Dcount)
Secure digital input/output interface (SDIO) RM0008 Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 0: Block data transfer 1: Stream or SDIO multibyte data transfer on STM32F10xxx XL-density devices. Stream data transfer on STM32F10xxx high-density devices. Bit 1 DTDIR: Data transfer direction selection 0: From controller to card.
Page 591: Sdio Status Register (Sdio_Sta)
RM0008 Secure digital input/output interface (SDIO) 22.9.11 SDIO status register (SDIO_STA) Address offset: 0x34 Reset value: 0x0000 0000 The SDIO_STA register is a read-only register. It contains two types of flag: ● Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDIO Interrupt Clear register (see SDIO_ICR) ●...
Page 592: Sdio Interrupt Clear Register (Sdio_Icr)
Secure digital input/output interface (SDIO) RM0008 Bit 4 TXUNDERR: Transmit FIFO underrun error Bit 3 DTIMEOUT: Data timeout Bit 2 CTIMEOUT: Command response timeout The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed) Bit 0 CCRCFAIL: Command response received (CRC check failed) 22.9.12 SDIO interrupt clear register (SDIO_ICR)
Page 593 RM0008 Secure digital input/output interface (SDIO) Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared Bit 5 RXOVERRC: RXOVERR flag clear bit...
Page 594: Sdio Mask Register (Sdio_Mask)
Secure digital input/output interface (SDIO) RM0008 22.9.13 SDIO mask register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24...
Page 595 RM0008 Secure digital input/output interface (SDIO) Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
Page 596: Sdio Fifo Counter Register (Sdio_Fifocnt)
Secure digital input/output interface (SDIO) RM0008 Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
Page 597: Sdio Data Fifo Register (Sdio_Fifo)
RM0008 Secure digital input/output interface (SDIO) 22.9.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
Page 598 Secure digital input/output interface (SDIO) RM0008 Table 167. SDIO register map (continued) Offset Register 0x38 SDIO_ICR 0x3C SDIO_MASK 0x48 SDIO_FIFOCNT Reserved FIFOCOUNT 0x80 SDIO_FIFO FIF0Data Refer to Table 3 on page 50 for the register boundary addresses. 598/1096 Doc ID 13902 Rev 12...
Page 599: Universal Serial Bus Full-Speed Device Interface (Usb)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 600: Figure 219. Usb Peripheral Block Diagram
Universal serial bus full-speed device interface (USB) RM0008 Figure 219. USB peripheral block diagram USB clock (48 MHz) Analog transceiver PCLK1 Control Clock RX-TX registers & logic recovery Suspend timer Control Endpoint Interrupt selection registers & logic S.I.E. Packet buffer Endpoint Endpoint interface...
Page 601: Description Of Usb Blocks
RM0008 Universal serial bus full-speed device interface (USB) proper handshake packet over the USB is generated or expected according to the direction of the transfer. At the end of the transaction, an endpoint-specific interrupt is generated, reading status registers and/or using different interrupt response routines. The microcontroller can determine: ●...
Page 602: Programming Considerations
Universal serial bus full-speed device interface (USB) RM0008 ● Control Registers: These are the registers containing information about the status of the whole USB peripheral and used to force some USB events, such as resume and power-down. ● Interrupt Registers: These contain the Interrupt masks and a record of the events. They can be used to inquire an interrupt reason, the interrupt status or to clear the status of a pending interrupt.
Page 603: System And Power-On Reset
RM0008 Universal serial bus full-speed device interface (USB) 23.4.2 System and power-on reset Upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the USB peripheral and subsequently de-assert its reset signal so to be able to access its registers.
Page 604: Figure 220. Packet Buffer Areas With Examples Of Buffer Description Table Locations
Universal serial bus full-speed device interface (USB) RM0008 clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different from the clock used for the interface to the APB1 bus. Different clock configurations are possible where the APB1 clock frequency can be higher or lower than the USB peripheral one.
Page 605 RM0008 Universal serial bus full-speed device interface (USB) Each packet buffer is used either during reception or transmission starting from the bottom. The USB peripheral will never change the contents of memory locations adjacent to the allocated memory buffers; if a packet bigger than the allocated buffer length is received (buffer overrun condition) the data will be copied to the memory only up to the last available location.
Page 606 Universal serial bus full-speed device interface (USB) RM0008 condition: the USB host will retry the transaction until it succeeds. It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second IN transaction addressed to the same endpoint immediately following the one which triggered the CTR interrupt.
Page 607 RM0008 Universal serial bus full-speed device interface (USB) STAT_RX bits are equal to ‘10 (NAK), any OUT request addressed to that endpoint is NAKed, indicating a flow control condition: the USB host will retry the transaction until it succeeds. It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second OUT transaction addressed to the same endpoint following immediately the one which triggered the CTR interrupt.
Page 608: Double-Buffered Endpoints
Universal serial bus full-speed device interface (USB) RM0008 23.4.3 Double-buffered endpoints All different endpoint types defined by the USB standard represent different traffic models, and describe the typical requirements of different kind of data transfer operations. When large portions of data are to be transferred between the host PC and the USB function, the bulk endpoint type is the most suited model.
Page 609: Table 168. Double-Buffering Buffer Flag Definition
RM0008 Universal serial bus full-speed device interface (USB) Table 168. Double-buffering buffer flag definition Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint DTOG DTOG_TX (USB_EPnRbit 6) DTOG_RX (USB_EPnRbit 14) SW_BUF USB_EPnR bit 14 USB_EPnR bit 6 The memory buffer which is currently being used by the USB peripheral is defined by DTOG buffer flag, while the buffer currently in use by application software is identified by SW_BUF buffer flag.
Page 610: Isochronous Transfers
Universal serial bus full-speed device interface (USB) RM0008 DBL_BUF setting, STAT bit pair is not affected by the transaction termination and its value remains ‘11 (Valid). However, as the token packet of a new transaction is received, the actual endpoint status will be masked as ‘10 (NAK) when a buffer conflict between the USB peripheral and the application software is detected (this condition is identified by DTOG and SW_BUF having the same value, see Table 169 on page...
Page 611: Suspend/Resume Events
RM0008 Universal serial bus full-speed device interface (USB) Table 170. Isochronous memory buffers usage Endpoint DTOG bit Packet buffer used by the Packet buffer used by the Type value USB peripheral application software ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1 buffer description table buffer description table locations.
Page 612: Table 171. Resume Event Detection
Universal serial bus full-speed device interface (USB) RM0008 The actual procedure used to suspend the USB peripheral is device dependent since according to the device composition, different actions may be required to reduce the total consumption. A brief description of a typical suspend procedure is provided below, focused on the USB- related aspects of the application software routine responding to the SUSP notification of the USB peripheral: Set the FSUSP bit in the USB_CNTR register to 1.
Page 613: Usb Registers
RM0008 Universal serial bus full-speed device interface (USB) A device may require to exit from suspend mode as an answer to particular events not directly related to the USB protocol (e.g. a mouse movement wakes up the whole system). In this case, the resume sequence can be started by setting the RESUME bit in the USB_CNTR register to ‘1 and resetting it to 0 after an interval between 1mS and 15mS (this interval can be timed using ESOF interrupts, occurring with a 1mS period when the system clock is running at nominal frequency).
Page 614: Common Registers
Universal serial bus full-speed device interface (USB) RM0008 23.5.1 Common registers These registers affect the general behavior of the USB peripheral defining operating mode, interrupt handling, device address and giving access to the current frame number updated by the host PC. USB control register (USB_CNTR) Address offset: 0x40 Reset value: 0x0003...
Page 615 RM0008 Universal serial bus full-speed device interface (USB) Bit 4 RESUME: Resume request The microcontroller can set this bit to send a Resume signal to the host. It must be activated, according to USB specifications, for no less than 1mS and no more than 15mS after which the Host PC is ready to drive the resume sequence up to its end.
Page 616 Universal serial bus full-speed device interface (USB) RM0008 USB interrupt status register (USB_ISTR) Address offset: 0x44 Reset value: 0x0000 0000 WKUP SUSP RESET ESOF EP_ID[3:0] Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 This register contains the status of all the interrupt sources allowing application software to determine, which events caused an interrupt request.
Page 617 RM0008 Universal serial bus full-speed device interface (USB) The following describes each bit in detail: Bit 15 CTR: Correct transfer This bit is set by the hardware to indicate that an endpoint has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint requested the interrupt.
Page 618 Universal serial bus full-speed device interface (USB) RM0008 Bit 10 RESET: USB reset request Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB peripheral, in response to a RESET, just resets its internal protocol state machine, generating an interrupt if RESETM enable bit in the USB_CNTR register is set.
Page 619 RM0008 Universal serial bus full-speed device interface (USB) USB frame number register (USB_FNR) Address offset: 0x48 Reset value: 0x0XXX where X is undefined RXDP RXDM LSOF[1:0] FN[10:0] Bit 15 RXDP: Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event.
Page 620 Universal serial bus full-speed device interface (USB) RM0008 USB device address (USB_DADDR) Address offset: 0x4C Reset value: 0x0000 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Reserved Bits 15:8 Reserved Bit 7 EF: Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits.
Page 621: Endpoint-Specific Registers
RM0008 Universal serial bus full-speed device interface (USB) 23.5.2 Endpoint-specific registers The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0.
Page 622 Universal serial bus full-speed device interface (USB) RM0008 Bit 15 CTR_RX: Correct Transfer for reception This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated.
Page 623 RM0008 Universal serial bus full-speed device interface (USB) Bits 10:9 EP_TYPE[1:0]: Endpoint type These bits configure the behavior of this endpoint as described in Table 173: Endpoint type encoding on page 624. Endpoint 0 must always be a control endpoint and each USB function must have at least one control endpoint which has address 0, but there may be other control endpoints if required.
Page 624: Table 172. Reception Status Encoding
Universal serial bus full-speed device interface (USB) RM0008 Bits 5:4 STAT_TX [1:0]: Status bits, for transmission transfers These bits contain the information about the endpoint status, listed in Table 175. These bits can be toggled by the software to initialize their value. When the application software writes ‘0, the value remains unchanged, while writing ‘1 makes the bit value toggle.
Page 625: Buffer Descriptor Table
RM0008 Universal serial bus full-speed device interface (USB) Table 175. Transmission status encoding STAT_TX[1:0] Meaning DISABLED: all transmission requests addressed to this endpoint are ignored. STALL: the endpoint is stalled and all transmission requests result in a STALL handshake. NAK: the endpoint is naked and all transmission requests result in a NAK handshake.
Page 626 Universal serial bus full-speed device interface (USB) RM0008 Transmission byte count n (USB_COUNTn_TX) Address offset: [USB_BTABLE] + n*16 + 4 USB local Address: [USB_BTABLE] + n*8 + 2 COUNTn_TX[9:0] Reserved Bits 15:10 These bits are not used since packet size is limited by USB specifications to 1023 bytes. Their value is not considered by the USB peripheral.
Page 627 RM0008 Universal serial bus full-speed device interface (USB) Reception byte count n (USB_COUNTn_RX) Address offset: [USB_BTABLE] + n*16 + 12 USB local Address: [USB_BTABLE] + n*8 + 6 BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0] This table location is used to store two different values, both required during packet reception.
Page 628: Usb Register Map
Universal serial bus full-speed device interface (USB) RM0008 Table 176. Definition of allocated buffer memory Value of Memory allocated Memory allocated NUM_BLOCK[4:0] when BL_SIZE=0 when BL_SIZE=1 0 (‘00000) Not allowed 32 bytes 1 (‘00001) 2 bytes 64 bytes 2 (‘00010) 4 bytes 96 bytes 3 (‘00011)
Page 629 RM0008 Universal serial bus full-speed device interface (USB) Table 177. USB register map and reset values (continued) Offset Register STAT_ STAT_ USB_EP6R TYPE EA[3:0] 0x18 Reserved [1:0] [1:0] [1:0] Reset value STAT_ STAT_ USB_EP7R TYPE EA[3:0] 0x1C Reserved [1:0] [1:0] [1:0] Reset value 0x20-...
Page 630: Controller Area Network (Bxcan)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 631: Bxcan General Description
RM0008 Controller area network (bxCAN) Time-triggered communication option ● Disable automatic retransmission mode ● 16-bit free running timer ● Time Stamp sent in last two data bytes Management ● Maskable interrupts ● Software-efficient mailbox mapping at a unique address space Dual CAN (connectivity line only) ●...
Page 632: Can 2.0B Active Core
Controller area network (bxCAN) RM0008 24.3.1 CAN 2.0B active core The bxCAN module handles the transmission and the reception of CAN messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware. 24.3.2 Control, status and configuration registers The application uses these registers to: ●...
Page 633: Bxcan Operating Modes
RM0008 Controller area network (bxCAN) Figure 222. Dual CAN block diagram (connectivity devices) CAN1 (Master) with 512 bytes SRAM Master Tx Mailboxes Receive FIFO 0 Receive FIFO 1 Mailbox 0 Mailbox 0 Mailbox 0 Master Control Master Status Tx Status Rx FIFO 0 Status Transmission Scheduler...
Page 634: Initialization Mode
Controller area network (bxCAN) RM0008 To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive bits have been monitored on CANRX. 24.4.1 Initialization mode The software initialization can be done while the hardware is in Initialization mode. To enter this mode the software sets the INRQ bit in the CAN_MCR register and waits until the hardware has confirmed the request by setting the INAK bit in the CAN_MSR register.
Page 635: Test Mode
RM0008 Controller area network (bxCAN) On CAN bus activity detection, hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit from Sleep mode.
Page 636: Loop Back Mode
Controller area network (bxCAN) RM0008 Figure 224. bxCAN in silent mode bxCAN CANTX CANRX 24.5.2 Loop back mode The bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR register. In Loop Back Mode, the bxCAN treats its own transmitted messages as received messages and stores them (if they pass acceptance filtering) in a Receive mailbox.
Page 637: Stm32F10Xxx In Debug Mode
RM0008 Controller area network (bxCAN) Figure 226. bxCAN in combined mode bxCAN CANTX CANRX 24.6 STM32F10xxx in Debug mode When the microcontroller enters the debug mode (Cortex-M3 core halted), the bxCAN continues to work normally or stops, depending on: ● the DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the DBG module.
Page 638: Figure 227. Transmit Mailbox States
Controller area network (bxCAN) RM0008 The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission. Abort A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR register.
Page 639: Time Triggered Communication Mode
RM0008 Controller area network (bxCAN) 24.7.2 Time triggered communication mode In this mode, the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to Section 24.7.7: Bit timing).
Page 640: Identifier Filtering
Controller area network (bxCAN) RM0008 FIFO management Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN_RFR register.
Page 641 RM0008 Controller area network (bxCAN) resources which would be otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0 and CAN_FxR1. Scalable width To optimize and adapt the filters to the application needs, each filter bank can be scaled independently.
Page 642: Figure 229. Filter Bank Scale Configuration - Register Organization
Controller area network (bxCAN) RM0008 Figure 229. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mask CAN_FxR2[31:24] CAN_FxR2[23:16] CAN_FxR2[15:8] CAN_FxR2[7:0] Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] Two 32-Bit Filters - Identifier List CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8]...
Page 643: Figure 230. Example Of Filter Numbering
RM0008 Controller area network (bxCAN) Figure 230. Example of filter numbering Filter Filter Filter Filter FIFO0 FIFO1 Bank Num. Bank Num. ID List (32-bit) ID Mask (16-bit) ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit)
Page 644: Message Storage
Controller area network (bxCAN) RM0008 Figure 231. Filtering mechanism - example Example of 3 filter banks in 32-bit Unidentified List mode and the remaining in 32-bit Identifier Mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier...
Page 645: Table 178. Transmit Mailbox Mapping
RM0008 Controller area network (bxCAN) Table 178. Transmit mailbox mapping Offset to transmit mailbox base address Register name CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox.
Page 646: Error Management
Controller area network (bxCAN) RM0008 24.7.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition.
Page 647: Figure 233. Bit Timing
RM0008 Controller area network (bxCAN) A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Page 648: Bxcan Interrupts
Controller area network (bxCAN) RM0008 Figure 234. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Ctrl Field Data Field CRC Field Ack Field Arbitration Field 8 * N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame...
Page 649: Figure 235. Event Flags And Interrupt Generation
RM0008 Controller area network (bxCAN) Figure 235. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT TMEIE RQCP0 & CAN_TSR RQCP1 RQCP2 FMPIE0 & FIFO 0 FMP0 INTERRUPT FFIE0 & CAN_RF0R FULL0 FOVIE0 & FOVR0 FMPIE1 & FIFO 1 FMP1 INTERRUPT FFIE1 &...
Page 650: Can Registers
Controller area network (bxCAN) RM0008 ● The error and status change interrupt can be generated by the following events: – Error condition, for more details on error conditions please refer to the CAN Error Status register (CAN_ESR). – Wakeup condition, SOF monitored on the CAN Rx signal. –...
Page 651 RM0008 Controller area network (bxCAN) Bit 15 RESET: bxCAN software master reset 0: Normal operation. 1: Force a master reset of the bxCAN -> Sleep mode activated after reset (FMP bits and CAN_MCR register are initialized to the reset values). This bit is automatically reset to 0. Bits 14:8 Reserved, forced by hardware to 0.
Page 652 Controller area network (bxCAN) RM0008 Bit 0 INRQ Initialization request The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception.
Page 653 RM0008 Controller area network (bxCAN) Bit 2 ERRI Error interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set.
Page 654 Controller area network (bxCAN) RM0008 Bit 27 TME1 Transmit mailbox 1 empty This bit is set by hardware when no transmit request is pending for mailbox 1. Bit 26 TME0 Transmit mailbox 0 empty This bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 CODE[1:0] Mailbox code In case at least one transmit mailbox is free, the code value is equal to the number of the...
Page 655 RM0008 Controller area network (bxCAN) Bit 8 RQCP1 Request completed mailbox1 Set by hardware when the last request (transmit or abort) has been performed. Cleared by software writing a “1” or by hardware on transmission request (TXRQ1 set in CAN_TI1R register). Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox 1.
Page 656 Controller area network (bxCAN) RM0008 Bit 4 FOVR0 FIFO 0 overrun This bit is set by hardware when a new message has been received and passed the filter while the FIFO was full. This bit is cleared by software. Bit 3 FULL0 FIFO 0 full Set by hardware when three messages are stored in the FIFO.
Page 657 RM0008 Controller area network (bxCAN) CAN interrupt enable register (CAN_IER) Address offset: 0x14 Reset value: 0x00 SLKIE WKUIE Reserved ERRIE Reserved Res. Bits 31:18 Reserved, forced by hardware to 0. Bit 17 SLKIE Sleep interrupt enable 0: No interrupt when SLAKI bit is set. 1: Interrupt generated when SLAKI bit is set.
Page 658 Controller area network (bxCAN) RM0008 Bit 4 FMPIE1 FIFO message pending interrupt enable 0: No interrupt generated when state of FMP[1:0] bits are not 00b. 1: Interrupt generated when state of FMP[1:0] bits are not 00b. Bit 3 FOVIE0 FIFO overrun interrupt enable 0: No interrupt when FOVR bit is set.
Page 659 RM0008 Controller area network (bxCAN) Bits 6:4 LEC[2:0] Last error code This field is set by hardware and holds a code which indicates the error condition of the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared to ‘0’.
Page 660: Can Mailbox Registers
Controller area network (bxCAN) RM0008 Bits 25:24 SJW[1:0] Resynchronization jump width These bits define the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform the resynchronization. x (SJW[1:0] + 1) Bit 23 Reserved, forced by hardware to 0.
Page 661 RM0008 Controller area network (bxCAN) CAN TX mailbox identifier register (CAN_TIxR) (x=0..2) Address offsets: 0x180, 0x190, 0x1A0 Reset value: undefined (except bit 0, TXRQ = 0) Note: All TX registers are write protected when the mailbox is pending transmission (TMEx reset). This register also implements the TX request control (bit 0) - reset value 0.
Page 662 Controller area network (bxCAN) RM0008 CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1A4 Reset value: undefined TIME[15:0] DLC[3:0] Reserved...
Page 663 RM0008 Controller area network (bxCAN) CAN mailbox data low register (CAN_TDLxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: undefined DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Bits 31:24 DATA3[7:0] Data byte 3 Data byte 3 of the message.
Page 664 Controller area network (bxCAN) RM0008 CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) Address offsets: 0x1B0, 0x1C0 Reset value: undefined Note: All RX registers are write protected. STID[10:0]/EXID[28:18] EXID[17:13] EXID[12:0] Res. Bits 31:21 STID[10:0]/EXID[28:18] Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value).
Page 665 RM0008 Controller area network (bxCAN) CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1) Address offsets: 0x1B4, 0x1C4 Reset value: undefined Note: All RX registers are write protected. TIME[15:0] FMI[7:0] DLC[3:0] Reserved Bits 31:16 TIME[15:0] Message time stamp This field contains the 16-bit timer value captured at the SOF detection.
Page 666 Controller area network (bxCAN) RM0008 CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1B8, 0x1C8 Reset value: undefined Note: All RX registers are write protected. DATA3[7:0] DATA2[7:0] DATA1[7:0]...
Page 667: Can Filter Registers
RM0008 Controller area network (bxCAN) Bits 15:8 DATA5[7:0] Data Byte 5 Data byte 1 of the message. Bits 7:0 DATA4[7:0] Data Byte 4 Data byte 0 of the message. 24.9.4 CAN filter registers CAN filter master register (CAN_FMR) Address offset: 0x200 Reset value: 0x2A1C 0E01 Note: All bits of this register are set and cleared by software.
Page 668 Controller area network (bxCAN) RM0008 CAN filter mode register (CAN_FM1R) Address offset: 0x204 Reset value: 0x00 Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. FBM27 FBM26 FBM25 FBM24 FBM23 FBM22 FBM21 FBM20 FBM19 FBM18 FBM17 FBM16 Reserved FBM15 FBM14 FBM13 FBM12 FBM11 FBM10 FBM9...
Page 669 RM0008 Controller area network (bxCAN) CAN filter FIFO assignment register (CAN_FFA1R) Address offset: 0x214 Reset value: 0x00 Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. FFA27 FFA26 FFA25 FFA24 FFA23 FFA22 FFA21...
Page 670 Controller area network (bxCAN) RM0008 Filter bank i register x (CAN_FiRx) (i=0..27 in connectivity line devices,, x=1, Address offsets: 0x240..0x31C Reset value: undefined Note: In connectivity line devices there are 28 filter banks, i=0 .. 27, in other devices there are 14 filter banks i = 0 ..13.
Page 671: Bxcan Register Map
RM0008 Controller area network (bxCAN) 24.9.5 bxCAN register map Refer to Table 3 on page 50 for the register boundary addresses. In connectivity line devices, the registers from offset 0x200 to 31C are present only in CAN1. Table 180. bxCAN register map and reset values Offset Register CAN_MCR...
Page 672 Controller area network (bxCAN) RM0008 Table 180. bxCAN register map and reset values (continued) Offset Register CAN_TDT1R TIME[15:0] DLC[3:0] 0x194 Reserved Reserved Reset value CAN_TDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x198 Reset value CAN_TDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x19C Reset value CAN_TI2R STID[10:0]/EXID[28:18] EXID[17:0]...
Page 673 RM0008 Controller area network (bxCAN) Table 180. bxCAN register map and reset values (continued) Offset Register CAN_FMR CAN2SB[5:0] 0x200 Reserved Reserved Reset value CAN_FM1R FBM[27:0] 0x204 Reserved Reset value 0x208 Reserved CAN_FS1R FSC[27:0] 0x20C Reserved Reset value 0x210 Reserved CAN_FFA1R FFA[27:0] 0x214 Reserved...
Page 674: Serial Peripheral Interface (Spi)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 675: Spi And I 2 S Main Features
RM0008 Serial peripheral interface (SPI) 25.2 SPI and I S main features 25.2.1 SPI features ● Full-duplex synchronous transfers on three lines ● Simplex synchronous transfers on two lines with or without a bidirectional data line ● 8- or 16-bit transfer frame format selection ●...
Page 676: I 2 S Features
Serial peripheral interface (SPI) RM0008 25.2.2 S features ● Simplex communication (only transmitter or receiver) ● Master or slave operations ● 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 96 kHz) ● Data format may be 16-bit, 24-bit or 32-bit ●...
Page 677: Spi Functional Description
RM0008 Serial peripheral interface (SPI) 25.3 SPI functional description 25.3.1 General description The block diagram of the SPI is shown in Figure 236. Figure 236. SPI block diagram Address and data bus Read Rx buffer SPI_CR2 MOSI RXNE TXDM RXDM SSOE Shift register MISO...
Page 678: Figure 237. Single Master/ Single Slave Application
Serial peripheral interface (SPI) RM0008 A basic example of interconnections between a single master and a single slave is illustrated in Figure 237. Figure 237. Single master/ single slave application Master Slave MSBit LSBit MSBit LSBit MISO MISO 8-bit shift register 8-bit shift register MOSI MOSI...
Page 679: Figure 238. Hardware/Software Slave Select Management
RM0008 Serial peripheral interface (SPI) Figure 238. Hardware/software slave select management SSM bit SSI bit NSS Internal NSS external pin ai14746 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register.
Page 680: Configuring The Spi In Slave Mode
Serial peripheral interface (SPI) RM0008 Figure 239. Data clock timing diagram 1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register. Data frame format Data can be shifted out either MSB-first or LSB-first depending on the value of the LSBFIRST bit in the SPI_CR1 Register.
Page 681 RM0008 Serial peripheral interface (SPI) Procedure Set the DFF bit to define 8- or 16-bit data frame format Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 239).
Page 682: Configuring The Spi In Master Mode
Serial peripheral interface (SPI) RM0008 25.3.3 Configuring the SPI in master mode In the master configuration, the serial clock is generated on the SCK pin. Procedure Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure...
Page 683: Configuring The Spi For Simplex Communication
RM0008 Serial peripheral interface (SPI) 25.3.4 Configuring the SPI for Simplex communication The SPI is capable of operating in simplex mode in 2 configurations. ● 1 clock and 1 bidirectional data wire ● 1 clock and 1 data wire (receive-only or transmit-only) 1 clock and 1 bidirectional data wire (BIDIMODE=1) This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register.
Page 684 Serial peripheral interface (SPI) RM0008 Start sequence in master mode ● In full-duplex (BIDIMODE=0 and RXONLY=0) – The sequence begins when data are written into the SPI_DR register (Tx buffer). – The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MOSI pin.
Page 685 RM0008 Serial peripheral interface (SPI) ● In bidirectional mode, when transmitting (BIDIMODE=1 and BIDIOE=1) – The sequence begins when the slave device receives the clock signal and the first bit in the Tx buffer is transmitted on the MISO pin. –...
Page 686: Figure 240. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0 And Rxonly=0)
Serial peripheral interface (SPI) RM0008 Figure 240. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers Example in Master mode with CPOL=1, CPHA=1 DATA1 = 0xF1 DATA2 = 0xF2 DATA3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware...
Page 687: Figure 242. Txe/Bsy Behavior In Master Transmit-Only Mode (Bidimode=0 And Rxonly=0) In The
RM0008 Serial peripheral interface (SPI) Transmit-only procedure (BIDIMODE=0 RXONLY=0) In this mode, the procedure can be reduced as described below and the BSY bit can be used to wait until the completion of the transmission (see Figure 242 Figure 243). Enable the SPI by setting the SPE bit to 1.
Page 688: Figure 243. Txe/Bsy In Slave Transmit-Only Mode (Bidimode=0 And Rxonly=0) In The Case Of
Serial peripheral interface (SPI) RM0008 Figure 243. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers Example in slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 689: Figure 244. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1) In The Case Of
RM0008 Serial peripheral interface (SPI) Figure 244. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of continuous transfers Example with CPOL=1, CPHA=1, RXONLY=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware cleared by software...
Page 690: Crc Calculation
Serial peripheral interface (SPI) RM0008 Figure 245. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of discontinuous transfers Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 TXE flag Tx buffer...
Page 691 RM0008 Serial peripheral interface (SPI) SPI communication using CRC is possible through the following procedure: ● Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values ● Program the polynomial in the SPI_CRCPR register ● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers ●...
Page 692: Status Flags
Serial peripheral interface (SPI) RM0008 25.3.7 Status flags Three status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can be loaded into the buffer.
Page 693: Disabling The Spi
RM0008 Serial peripheral interface (SPI) 25.3.8 Disabling the SPI When a transfer is terminated, the application can stop the communication by disabling the SPI peripheral. This is done by clearing the SPE bit. For some configurations, disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted and/or the BSY flag might become unreliable.
Page 694: Spi Communication Using Dma (Direct Memory Addressing)
Serial peripheral interface (SPI) RM0008 25.3.9 SPI communication using DMA (direct memory addressing) To operate at its maximum speed, the SPI needs to be fed with the data for transmission and the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers, the SPI features a DMA capability implementing a simple request/acknowledge protocol.
Page 695: Error Flags
RM0008 Serial peripheral interface (SPI) Figure 247. Reception using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware clear by DMA read RXNE flag...
Page 696: Spi Interrupts
Serial peripheral interface (SPI) RM0008 As a security, hardware does not allow the setting of the SPE and MSTR bits while the MODF bit is set. In a slave device the MODF bit cannot be set. However, in a multimaster configuration, the device can be in slave mode with this MODF bit set.
Page 697: S Functional Description
RM0008 Serial peripheral interface (SPI) 25.4 S functional description The I S audio protocol is not available in low- and medium-density devices. This section concerns only high-density, XL-density and connectivity line devices. 25.4.1 S general description The block diagram of the I S is shown in Figure 248.
Page 698: Supported Audio Protocols
Serial peripheral interface (SPI) RM0008 The I S shares three common pins with the SPI: ● SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time- multiplexed data channels (in simplex mode only). ● WS: Word Select (mapped on the NSS pin) is the data control signal output in master mode and input in slave mode.
Page 699: Figure 249. I 2 S Phillips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0008 Serial peripheral interface (SPI) The I S interface supports four audio standards, configurable using the I2SSTD[1:0] and PCMSYNC bits in the SPI_I2SCFGR register. S Phillips standard For this standard, the WS signal is used to indicate which channel is being transmitted. It is activated one CK clock cycle before the first bit (MSB) is available.
Page 700: Figure 251. Transmitting 0X8Eaa33
Serial peripheral interface (SPI) RM0008 Figure 251. Transmitting 0x8EAA33 Second write to Data register First write to Data register 0x8EAA 0x33XX Only the 8 MSBs are sent to complete the 24 bits 8 LSB bits have no meaning and could be anything ●...
Page 701: Figure 254. Example
RM0008 Serial peripheral interface (SPI) Figure 254. Example Only one access to SPI_DR 0X76A3 For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
Page 702: Figure 256. Msb Justified 24-Bit Frame Length With Cpol = 0
Serial peripheral interface (SPI) RM0008 Figure 256. MSB Justified 24-bit frame length with CPOL = 0 Reception Transmission 8-bit remaining 24-bit data 0 forced Channel left 32-bit Channel right Figure 257. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 Reception Transmission 16-bit remaining...
Page 703: Figure 259. Lsb Justified 24-Bit Frame Length With Cpol = 0
RM0008 Serial peripheral interface (SPI) Figure 259. LSB Justified 24-bit frame length with CPOL = 0 Reception Transmission 24-bit remaining 8-bit data 0 forced Channel left 32-bit Channel right ● In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register are required from software or by DMA.
Page 704: Figure 262. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
Serial peripheral interface (SPI) RM0008 Figure 262. LSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit remaining 16-bit data 0 forced Channel left 32-bit Channel right When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, Only one access to SPI_DR is required.
Page 705: Clock Generator
RM0008 Serial peripheral interface (SPI) Figure 264. PCM standard waveforms (16-bit) short frame up to 13-bit long frame 16-bit LSB MSB For long frame synchronization, the WS signal assertion time is fixed 13 bits in master mode. For short frame synchronization, the WS synchronization signal is only one cycle long. Figure 265.
Page 706: Figure 266. Audio Sampling Frequency Definition
Serial peripheral interface (SPI) RM0008 It will be: I S bitrate = 32 x 2 x F if the packet length is 32-bit wide. Figure 266. Audio sampling frequency definition 16-bit or 32-bit Left channel 16-bit or 32-bit Right channel 32-bits or 64-bits sampling point sampling point...
Page 707: Table 182. Audio-Frequency Precision Using Standard 8 Mhz Hse
RM0008 Serial peripheral interface (SPI) Note: Other configurations are possible that allow optimum clock precision. Table 182. Audio-frequency precision using standard 8 MHz HSE (high-density and XL-density devices only) I2S_DIV I2S_ODD Real f (KHz) Error SYSCLK Target f MCLK (MHz) (Hz) 16-bit 32-bit...
Page 708: (Connectivity Line Devices Only)
Serial peripheral interface (SPI) RM0008 Table 183. Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only) Data Target PREDIV2 PLL3MUL I2SDIV I2SODD MCLK Real fs (KHz) Error length fs(Hz) 96000 95942.9825 0.0594% 48000 47971.4912 0.0594% 48000 47971.4912 0.0594% 44100 44102.823...
Page 709: Table 184. Audio-Frequency Precision Using Standard 14.7456 Mhz And Pll3
RM0008 Serial peripheral interface (SPI) Table 184. Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only) Data Target Real fs PREDIV2 PLL3MUL I2SDIV I2SODD MCLK Error length fs(Hz) (KHz) 96000 96000 0.0000% 96000 96000 0.0000% 48000 48000 0.0000% 48000 48000...
Page 710: I 2 S Master Mode
Serial peripheral interface (SPI) RM0008 25.4.4 S master mode The I S can be configured in master mode. This means that the serial clock is generated on the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not, thanks to the MCKOE bit in the SPI_I2SPR register.
Page 711: I 2 S Slave Mode
RM0008 Serial peripheral interface (SPI) Reception sequence The operating mode is the same as for the transmission mode except for the point 3 (refer to the procedure described in Section 25.4.4: I2S master mode), where the configuration should set the master reception mode through the I2SCFG[1:0] bits. Whatever the data or channel length, the audio data are received by 16-bit packets.
Page 712 Serial peripheral interface (SPI) RM0008 clock and WS signals are input from the external master connected to the I S interface. There is then no need, for the user, to configure the clock. The configuration steps to follow are listed below: Set the I2SMOD bit in the SPI_I2SCFGR register to reach the I S functionalities and choose the I...
Page 713: Status Flags
RM0008 Serial peripheral interface (SPI) Reception sequence The operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in Section 25.4.5: I2S slave mode), where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPI_I2SCFGR register. Whatever the data length or the channel length, the audio data are received by 16-bit packets.
Page 714: Error Flags
Serial peripheral interface (SPI) RM0008 Tx buffer empty flag (TXE) When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to be transmitted.
Page 715: I 2 S Interrupts
RM0008 Serial peripheral interface (SPI) 25.4.8 S interrupts Table 185 provides the list of I S interrupts. Table 185. I S interrupt requests Interrupt event Event flag Enable Control bit Transmit buffer empty flag TXEIE Receive buffer not empty flag RXNE RXNEIE Overrun error...
Page 716: Spi And I 2 S Registers
Serial peripheral interface (SPI) RM0008 25.5 SPI and I S registers Refer to Section 2.1 on page 45 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 25.5.1 SPI control register 1 (SPI_CR1) (not used in I S mode) Address offset: 0x00...
Page 717 RM0008 Serial peripheral interface (SPI) Bit 10 RXONLY: Receive only This bit combined with the BIDImode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0: Full duplex (Transmit and receive) 1: Output disabled (Receive-only mode) Note: Not used in I...
Page 718 Serial peripheral interface (SPI) RM0008 Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing. Not used in I S mode Bit 0 CPHA: Clock phase 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge Note: This bit should not be changed when communication is ongoing.
Page 719: Spi Control Register 2 (Spi_Cr2)
RM0008 Serial peripheral interface (SPI) 25.5.2 SPI control register 2 (SPI_CR2) Address offset: 0x04 Reset value: 0x0000 TXEIE RXNEIE ERRIE Res. Res. SSOE TXDMAEN RXDMAEN Reserved Bits 15:8 Reserved. Forced to 0 by hardware. Bit 7 TXEIE: Tx buffer empty interrupt enable 0: TXE interrupt masked 1: TXE interrupt not masked.
Page 720: Spi Status Register (Spi_Sr)
Serial peripheral interface (SPI) RM0008 25.5.3 SPI status register (SPI_SR) Address offset: 0x08 Reset value: 0x0002 CHSID MODF RXNE Reserved rc_w0 Bits 15:8 Reserved. Forced to 0 by hardware. Bit 7 BSY: Busy flag 0: SPI (or I2S)not busy 1: SPI (or I2S)is busy in communication or Tx buffer is not empty This flag is set and cleared by hardware.
Page 721: Spi Data Register (Spi_Dr)
RM0008 Serial peripheral interface (SPI) 25.5.4 SPI data register (SPI_DR) Address offset: 0x0C Reset value: 0x0000 DR[15:0] Bits 15:0 DR[15:0]: Data register Data received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for reading (Receive buffer).
Page 722: Spi Rx Crc Register (Spi_Rxcrcr)
Serial peripheral interface (SPI) RM0008 25.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I S mode) Address offset: 0x14 Reset value: 0x0000 RXCRC[15:0] Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes.
Page 723: Spi_I 2 S Configuration Register (Spi_I2Scfgr)
RM0008 Serial peripheral interface (SPI) 25.5.8 SPI_I S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 PCMSY I2SMOD I2SE I2SCFG I2SSTD CKPOL DATLEN CHLEN Reserved Reserved Bits 15:12 Reserved: Forced to 0 by hardware Bit 11 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S mode is selected Note: This bit should be configured when the SPI or I...
Page 724: Spi_I 2 S Prescaler Register (Spi_I2Spr)
Serial peripheral interface (SPI) RM0008 Bit 2:1 DATLEN: Data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed Note: For correct operation, these bits should be configured when the I S is disabled.
Page 725: Spi Register Map
RM0008 Serial peripheral interface (SPI) 25.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 186. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset value SPI_CR2 0x04 Reserved Reset value SPI_SR 0x08...
Page 726: Inter-Integrated Circuit (I 2 C) Interface
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 727: I 2 C Functional Description
RM0008 Inter-integrated circuit (I C) interface – C busy flag ● Error flags: – Arbitration lost condition for master mode – Acknowledgement failure after address/ data transmission – Detection of misplaced start or stop condition – Overrun/Underrun if clock stretching is disabled ●...
Page 728: Figure 268. I2C Bus Protocol
Inter-integrated circuit (I C) interface RM0008 Communication flow In Master mode, the I C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software.
Page 729: I2C Slave Mode
RM0008 Inter-integrated circuit (I C) interface Figure 269. I C block diagram Data register Data Data shift register control PEC calculation Comparator Own address register Dual address register Clock PEC register control Clock control Register (CCR) Control registers (CR1&CR2) Control Status registers logic (SR1&SR2)
Page 730: Figure 270. Transfer Sequence Diagram For Slave Transmitter
Inter-integrated circuit (I C) interface RM0008 Address matched: the interface generates in sequence: ● An acknowledge pulse if the ACK bit is set ● The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Page 731: I2C Master Mode
RM0008 Inter-integrated circuit (I C) interface Slave receiver Following the address reception and after clearing ADDR, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ●...
Page 732 Inter-integrated circuit (I C) interface RM0008 The following is the required sequence in master mode. ● Program the peripheral input clock in I2C_CR2 Register in order to generate correct timings ● Configure the clock control registers ● Configure the rise time register ●...
Page 733 RM0008 Inter-integrated circuit (I C) interface Start condition Setting the START bit causes the interface to generate a Start condition and to switch to Master mode (M/SL bit set) when the BUSY bit is cleared. Note: In master mode, setting the START bit causes the interface to generate a ReStart condition at the end of the current byte transfer.
Page 734: Figure 272. Transfer Sequence Diagram For Master Transmitter
Inter-integrated circuit (I C) interface RM0008 Master transmitter Following the address transmission and after clearing ADDR, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits until the first data byte is written into I2C_DR (see Figure 272 Transfer sequencing EV8_1).
Page 735 RM0008 Inter-integrated circuit (I C) interface Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 736: Figure 273. Method 1: Transfer Sequence Diagram For Master Receiver
Inter-integrated circuit (I C) interface RM0008 Figure 273. Method 1: transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3.
Page 737: Figure 274. Method 2: Transfer Sequence Diagram For Master Receiver When N>2
RM0008 Inter-integrated circuit (I C) interface Figure 274. Method 2: transfer sequence diagram for master receiver when N>2 7- bit master receiver Address Data1 Data2 DataN-2 DataN-1 DataN EV7_2 10- bit master receiver Header Address Header Data1 Data2 DataN-2 DataN-1 DataN EV7_2 Legend: S = Start, S...
Page 738: Figure 275. Method 2: Transfer Sequence Diagram For Master Receiver When N=2
Inter-integrated circuit (I C) interface RM0008 The procedure described above is valid for N>2. The cases where a single byte or two bytes are to be received should be handled differently, as described below: ● Case of a single byte to be received: –...
Page 739: Error Conditions
RM0008 Inter-integrated circuit (I C) interface Figure 276. Method 2: transfer sequence diagram for master receiver when N=1 7- bit master receiver Address Data1 EV6_3 10- bit master receiver Header Address Header Data1 EV6_3 Legend: S = Start, S = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.
Page 740: Sda/Scl Line Control
Inter-integrated circuit (I C) interface RM0008 Arbitration lost (ARLO) This error occurs when the I C interface detects an arbitration lost condition. In this case, ● the ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is set) ●...
Page 741: Smbus
RM0008 Inter-integrated circuit (I C) interface 26.3.6 SMBus Introduction The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I principles of operation. SMBus provides a control bus for system and power management related tasks.
Page 742 Inter-integrated circuit (I C) interface RM0008 Bus protocols The SMBus specification supports up to 9 bus protocols. For more details of these protocols and SMBus address types, refer to SMBus specification ver. 2.0 (http://smbus.org/specs/). These protocols should be implemented by the user software. Address resolution protocol (ARP) SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device.
Page 743: Dma Requests
RM0008 Inter-integrated circuit (I C) interface Timeout error There are differences in the timing specifications between I C and SMBus. SMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device.
Page 744 Inter-integrated circuit (I C) interface RM0008 Set the I2C_DR register address in the DMA_CPARx register. The data will be moved to this address from the memory after each TxE event. Set the memory address in the DMA_CMARx register. The data will be loaded into I2C_DR from this memory after each TxE event.
Page 745: Packet Error Checking
RM0008 Inter-integrated circuit (I C) interface 26.3.8 Packet error checking A PEC calculator has been implemented to improve the reliability of communication. The PEC is calculated by using the C(x) = x + x + 1 CRC-8 polynomial serially on each bit. ●...
Page 746: Figure 277. I2C Interrupt Mapping Diagram
Inter-integrated circuit (I C) interface RM0008 Table 188. I C Interrupt requests (continued) Interrupt event Event flag Enable control bit Bus error BERR Arbitration loss (Master) ARLO Acknowledge failure Overrun/Underrun ITERREN PEC error PECERR Timeout/Tlow error TIMEOUT SMBus Alert SMBALERT Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt channel.
Page 747: I 2 C Debug Mode
RM0008 Inter-integrated circuit (I C) interface 26.5 C debug mode When the microcontroller enters the debug mode (Cortex-M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C on page...
Page 748 Inter-integrated circuit (I C) interface RM0008 Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 749: Control Register 2 (I2C_Cr2)
RM0008 Inter-integrated circuit (I C) interface Bit 4 ENARP: ARP enable 0: ARP disable 1: ARP enable SMBus Device default address recognized if SMBTYPE=0 SMBus Host address recognized if SMBTYPE=1 Bit 3 SMBTYPE: SMBus type 0: SMBus Device 1: SMBus Host Bit 2 Reserved, forced by hardware to 0.
Page 750: Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I C) interface RM0008 Bit 9 ITEVTEN: Event interrupt enable 0: Event interrupt disabled 1: Event interrupt enabled This interrupt is generated when: –SB = 1 (Master) –ADDR = 1 (Master/Slave) –ADD10= 1 (Master) –STOPF = 1 (Slave) –BTF = 1 with no TxE or RxNE event –TxE event to 1 if ITBUFEN = 1 –RxNE event to 1if ITBUFEN = 1...
Page 751: Own Address Register 2 (I2C_Oar2)
RM0008 Inter-integrated circuit (I C) interface Bits 13:10 Reserved, forced by hardware to 0. Bits 9:8 ADD[9:8]: Interface address 7-bit addressing mode: don’t care 10-bit addressing mode: bits9:8 of address Bits 7:1 ADD[7:1]: Interface address bits 7:1 of address Bit 0 ADD0: Interface address 7-bit addressing mode: don’t care 10-bit addressing mode: bit 0 of address 26.6.4...
Page 752: Status Register 1 (I2C_Sr1)
Inter-integrated circuit (I C) interface RM0008 26.6.6 Status register 1 (I2C_SR1) Address offset: 0x14 Reset value: 0x0000 TIME ARLO BERR RxNE STOPF ADD10 ADDR ALERT Res. Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode:...
Page 753 RM0008 Inter-integrated circuit (I C) interface Bit 10 AF: Acknowledge failure 0: No acknowledge failure 1: Acknowledge failure –Set by hardware when no acknowledge is returned. –Cleared by software writing 0, or by hardware when PE=0. Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master...
Page 754 Inter-integrated circuit (I C) interface RM0008 Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). –Set by hardware when the master has sent the first byte in 10-bit address mode. –Cleared by software reading the SR1 register followed by a write in the DR register of the second address byte, or by hardware when PE=0.
Page 755: Status Register 2 (I2C_Sr2)
RM0008 Inter-integrated circuit (I C) interface 26.6.7 Status register 2 (I2C_SR2) Address offset: 0x18 Reset value:0x0000 SMBDE PEC[7:0] DUALF BUSY HOST FAULT CALL Res. Bits 15:8 PEC[7:0] Packet error checking register This register contains the internal PEC when ENPEC=1. Bit 7 DUALF: Dual flag (Slave mode) 0: Received address matched with OAR1 1: Received address matched with OAR2 –Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.
Page 756: Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I C) interface RM0008 Bit 0 MSL: Master/slave 0: Slave Mode 1: Master Mode –Set by hardware as soon as the interface is in Master mode (SB=1). –Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1), or by hardware when PE=0.
Page 757: Trise Register (I2C_Trise)
RM0008 Inter-integrated circuit (I C) interface 26.6.9 TRISE register (I2C_TRISE) Address offset: 0x20 Reset value: 0x0002 TRISE[5:0] Reserved Bits 15:6 Reserved, forced by hardware to 0. Bits 5:0 TRISE[5:0]: Maximum rise time in Fast/Standard mode (Master mode) These bits must be programmed with the maximum SCL rise time given in the I C bus specification, incremented by 1.
Page 758: I2C Register Map
Inter-integrated circuit (I C) interface RM0008 26.6.10 C register map The table below provides the I C register map and reset values. Table 189. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value...
Page 759: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 760: Usart Main Features
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.2 USART main features ● Full duplex, asynchronous communications ● NRZ standard format (Mark/Space) ● Fractional baud rate generator systems – A common programmable transmit and receive baud rates up to 4.5 MBits/s ●...
Page 761: Usart Functional Description
RM0008 Universal synchronous asynchronous receiver transmitter (USART) ● Parity control: – Transmits parity bit – Checks parity of received data byte ● Four error detection flags: – Overrun error – Noise error – Frame error – Parity error ● Ten interrupt sources with flags: –...
Page 762 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: ● An Idle Line prior to transmission or reception ● A start bit ● A data word (8 or 9 bits) least significant bit first ●...
Page 763: Usart Block Diagramusart Character Description
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.1 USART character description USART block diagram PRDATA PWDATA Write Read (DATA REGISTER) DR (CPU or DMA) (CPU or DMA) Receive Data Register (RDR) Transmit Data Register (TDR) IrDA SW_RX ENDEC Receive Shift Register Transmit Shift Register BLOCK IRDA_OUT...
Page 764: Figure 278. Word Length Programming
Universal synchronous asynchronous receiver transmitter (USART) RM0008 A Break character is interpreted on receiving “0”s for a frame period. At the end of the break frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the start bit.
Page 765: Transmitter
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Page 766: Figure 279. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 279. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 767: Figure 280. Tc/Txe Behavior When Transmitting
RM0008 Universal synchronous asynchronous receiver transmitter (USART) When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 768: Receiver
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.3.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.
Page 769 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Character reception During a USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register.
Page 770: Figure 282. Data Sampling For Noise Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0008 The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: ●...
Page 771: Table 190. Noise Detection From Sampled Data
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Table 190. Noise detection from sampled data Sampled value NE status Received bit value Data validity Valid Not Valid Not Valid Not Valid Not Valid Not Valid Not Valid Valid When noise is detected in a frame: ●...
Page 772: Fractional Baud Rate Generation
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit.
Page 773: Table 191. Error Calculation For Programmed Baud Rates
RM0008 Universal synchronous asynchronous receiver transmitter (USART) This leads to: DIV_Fraction = 16*0d0.62 = 0d9.92 The nearest real number is 0d10 = 0xA DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19 Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625 Example 3: To program USARTDIV = 0d50.99 This leads to: DIV_Fraction = 16*0d0.99 = 0d15.84...
Page 774: Usart Receiver's Tolerance To Clock Deviation
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.3.5 USART receiver’s tolerance to clock deviation The USART’s asynchronous receiver works correctly only if the total clock system deviation is smaller than the USART receiver’s tolerance. The causes which contribute to the total deviation are: ●...
Page 775: Figure 283. Mute Mode Using Idle Line Detection
RM0008 Universal synchronous asynchronous receiver transmitter (USART) The non addressed devices may be placed in mute mode by means of the muting function. In mute mode: ● None of the reception status bits can be set. ● All the receive interrupts are inhibited. ●...
Page 776: Parity Control
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 284. Mute mode using Address mark detection In this example, the current address of the receiver is 1 RXNE RXNE (programmed in the USART_CR2 register) IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2...
Page 777: Lin (Local Interconnection Network) Mode
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.8 LIN (local interconnection network) mode The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: ● CLKEN in the USART_CR2 register, ●...
Page 778: Figure 285. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 285. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBD is not set Break frame RX line Capture Strobe Break State machine Idle...
Page 779: Usart Synchronous Mode
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 286. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK...
Page 780: Figure 287. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR has been written).
Page 781: Single-Wire Half-Duplex Communication
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 289. USART data clock timing diagram (M=1) Idle or preceding Start transmission M=1 (9 data bits) Idle or next Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop...
Page 782: Smartcard
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Apart from this, the communications are similar to what is done in normal USART mode. The conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set.
Page 783 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Smartcard is a single wire half duplex communication protocol. ● Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation a full transmit shift register will start shifting on the next baud clock edge.
Page 784: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 292. Parity error detection using the 1.5 stop bits Bit 7 Parity Bit 1.5 Stop Bit 1 bit time 1.5 bit time sampling at sampling at 16th, 17th, 18th 8th, 9th, 10th 0.5 bit time 1 bit time sampling at...
Page 785 RM0008 Universal synchronous asynchronous receiver transmitter (USART) ● IrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USARTsends data to the IrDA encoder), any data on the IrDA receive line is ignored by the IrDA decoder and if the Receiver is busy (USART receives decoded data from the USART), data on the TX from the USART to IrDA is not encoded by IrDA.
Page 786: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 293. IrDA SIR ENDEC- block diagram USART_TX Transmit IrDA_OUT SIREN Encoder USART IrDA_IN Receive Decoder USART_RX Figure 294. IrDA data modulation (3/16) -normal mode stop bit Start bit period IrDA_OUT 3/16 IrDA_IN 27.3.13 Continuous communication using DMA The USART is capable of continuing communication using the DMA.
Page 787: Figure 295. Transmission Using Dma
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Write the USART_DR register address in the DMA control register to configure it as the destination of the transfer. The data will be moved to this address from memory after each TXE event. Write the memory address in the DMA control register to configure it as the source of the transfer.
Page 788: Figure 296. Reception Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 789: Hardware Flow Control
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.14 Hardware flow control It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. The Figure 297 shows how to connect 2 devices in this mode: Figure 297.
Page 790: Usart Interrupts
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 299. CTS flow control nCTS Transmit data register Data 2 empty Data 3 empty Stop Start Stop Idle Start Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until nCTS = 0 27.4 USART interrupts...
Page 791: Usart Mode Configuration
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 300. USART interrupt mapping diagram TCIE TXEIE CTSIE USART IDLE interrupt IDLEIE RXNEIE RXNEIE RXNE PEIE LBDIE DMAR 27.5 USART mode configuration Table 196. USART mode configuration USART modes USART1 USART2 USART3 UART4 UART5 Asynchronous mode...
Page 792: Status Register (Usart_Sr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.6.1 Status register (USART_SR) Address offset: 0x00 Reset value: 0x00C0 Reserved RXNE IDLE Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:10 Reserved, forced by hardware to 0. Bit 9 CTS: CTS flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set.
Page 793 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 4 IDLE: IDLE line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the IDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register).
Page 794: Data Register (Usart_Dr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: Undefined Reserved DR[8:0] Reserved Bits 31:9 Reserved, forced by hardware to 0. Bits 8:0 DR[8:0]: Data value Contains the Received or Transmitted data character, depending on whether it is read from or written to.
Page 795: Control Register 1 (Usart_Cr1)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 Reserved WAKE PEIE TXEIE TCIE RXNEIE IDLEIE Reserved Bits 31:14 Reserved, forced by hardware to 0. Bit 13 UE: USART enable When this bit is cleared the USART prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.
Page 796 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever TC=1 in the USART_SR register Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software.
Page 797: Control Register 2 (Usart_Cr2)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 Reserved LINEN STOP[1:0] CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Res. Bits 31:15 Reserved, forced by hardware to 0. Bit 14 LINEN: LIN mode enable This bit is set and cleared by software.
Page 798: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the CK pin 1: The clock pulse of the last data bit is output to the CK pin The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 799 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 RTSE: RTS enable 0: RTS hardware flow control disabled 1: RTS interrupt enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted.
Page 800: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.6.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 Reserved GT[7:0] PSC[7:0] Bits 31:16 Reserved, forced by hardware to 0. Bits 15:8 GT[7:0]: Guard time value This bit-field gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode.
Page 801: Usart Register Map
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.6.8 USART register map The table below gives the USART register map and reset values. Table 197. USART register map and reset values Offset Register USART_SR 0x00 Reserved Reset value USART_DR DR[8:0] 0x04 Reserved Reset value DIV_Fraction...
Page 802: Usb On-The-Go Full-Speed (Otg_Fs)
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 803: Otg_Fs Main Features
RM0008 USB on-the-go full-speed (OTG_FS) 28.2 OTG_FS main features The main features can be divided into three categories: general, host-mode and device- mode features. 28.2.1 General features The OTG_FS interface general features are the following: ● It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0 ●...
Page 804: Host-Mode Features
USB on-the-go full-speed (OTG_FS) RM0008 28.2.2 Host-mode features The OTG_FS interface main features and requirements in host-mode are the following: ● External charge pump for V voltage generation. ● Up to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer.
Page 805: Otg_Fs Functional Description
RM0008 USB on-the-go full-speed (OTG_FS) 28.3 OTG_FS functional description Figure 301. Block diagram Cortex-M3 USB Interrupt USB2.0 Power& OTG FS Clock UTMIFS Core CTRL USB duspend System clock USB clock USB Clock at 48 MHz domain domain Universal serial bus 1.25 Kbytes USB data FIFOs...
Page 806: Otg Dual Role Device (Drd)
USB on-the-go full-speed (OTG_FS) RM0008 the physical support to USB connectivity. The full-speed OTG PHY includes the following components: ● FS/LS transceiver module used by both host and device. It directly drives transmission and reception on the single-ended USB lines. ●...
Page 807: Id Line Detection
RM0008 USB on-the-go full-speed (OTG_FS) 28.4.1 ID line detection The host or peripheral (the default) role is assumed depending on the ID input pin. The ID line status is determined on plugging in the USB, depending on which side of the USB cable is connected to the micro-AB receptacle.
Page 808: Usb Peripheral
USB on-the-go full-speed (OTG_FS) RM0008 28.5 USB peripheral This section gives the functional description of the OTG_FS in the USB peripheral mode. The OTG_FS works as an USB peripheral in the following circumstances: ● OTG B-Peripheral – OTG B-device default state if B-side of USB cable is plugged in ●...
Page 809: Peripheral States
RM0008 USB on-the-go full-speed (OTG_FS) In this way, it allows the remote A-device to save power by switching off V while the USB session is suspended. The SRP peripheral mode program model is described in detail in the B-device session request protocol section.
Page 810: Peripheral Endpoints
USB on-the-go full-speed (OTG_FS) RM0008 When a resume signaling is detected from the host, the resume interrupt (RWUSIG bit in OTG_FS_GINTSTS) is generated and the device suspend bit is automatically cleared. 28.5.3 Peripheral endpoints The OTG_FS core instantiates the following USB endpoints: ●...
Page 811 RM0008 USB on-the-go full-speed (OTG_FS) Endpoint control ● The following endpoint controls are available to the application through the device endpoint-x IN/OUT control register (DIEPCTLx/DOEPCTLx): – Endpoint enable/disable – Endpoint activate in current configuration – Program USB transfer type (isochronous, bulk, interrupt) –...
Page 812: Usb Host
USB on-the-go full-speed (OTG_FS) RM0008 The peripheral core provides the following status checks and interrupt generation: ● Transfer completed interrupt, indicating that data transfer was completed on both the application (AHB) and USB sides ● Setup stage has been done (control-out only) ●...
Page 813: Srp-Capable Host
RM0008 USB on-the-go full-speed (OTG_FS) Figure 304. USB host-only connection 1. STMPS2141STR needed only if the application has to support a V powered device. A basic power switch can be used if 5 V are available on the application board. 28.6.1 SRP-capable host SRP support is available through the SRP capable bit in the global USB configuration...
Page 814: Host Channels
USB on-the-go full-speed (OTG_FS) RM0008 When V is at a valid level and a remote B-device is attached, the OTG_FS core issues a host port interrupt triggered by the device connected bit in the host port control and status register (PCDET bit in OTG_FS_HPRT). Host detection of peripheral a disconnection The peripheral disconnection event triggers the disconnect detected interrupt (DISCINT bit in OTG_FS_GINTSTS).
Page 815 RM0008 USB on-the-go full-speed (OTG_FS) Each host channel can be configured to support in/out and any type of periodic/nonperiodic transaction. Each host channel makes us of proper control (HCCHARx), transfer configuration (HCTSIZx) and status/interrupt (HCINTx) registers with associated mask (HCINTMSKx) registers. Host channel control ●...
Page 816: Host Scheduler
USB on-the-go full-speed (OTG_FS) RM0008 corresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt source of each channel are also available in the OTG_FS_HCINTMSK-x register. ● The host core provides the following status checks and interrupt generation: –...
Page 817: Sof Trigger
RM0008 USB on-the-go full-speed (OTG_FS) PTXQSAV bits in the OTG_FS_HNPTXSTS register or NPTQXSAV bits in the OTG_FS_HNPTXSTS register. 28.7 SOF trigger Figure 305. SOF connectivity STM32F105xx STM32F107xx SOF pulse output, to external audio control VBUS PA11 ITR1 pulse PA12 SOFgen TIM2 PA10 ai17120...
Page 818: Power Options
USB on-the-go full-speed (OTG_FS) RM0008 register (SOFOUTEN bit in OTG_FS_GCCFG). The SOF pulse signal is also internally connected to the TIM2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled by bit 29 in the AFIO_MAPR register.
Page 819: Dynamic Update Of The Otg_Fs_Hfir Register
RM0008 USB on-the-go full-speed (OTG_FS) To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS core. 28.9 Dynamic update of the OTG_FS_HFIR register The USB core embeds a dynamic trimming capability of micro-SOF framing period in host mode allowing to synchronize an external device with the micro-SOF frames.
Page 820: Peripheral Fifo Architecture
USB on-the-go full-speed (OTG_FS) RM0008 28.11 Peripheral FIFO architecture Figure 307. Device-mode FIFO address mapping and AHB FIFO access mapping Single data FIFO DIEPTXF2[31:16] IN endpoint Tx FIFO #n Dedicated Tx Tx FIFO #n DFIFO push access packet FIFO #n control DIEPTXFx[15:0] from AHB (optional)
Page 821: Peripheral Tx Fifos
RM0008 USB on-the-go full-speed (OTG_FS) 28.11.2 Peripheral Tx FIFOs The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the non periodic transmit FIFO size register (OTG_FS_TX0FSIZ) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x. 28.12 Host FIFO architecture Figure 308.
Page 822: Host Tx Fifos
USB on-the-go full-speed (OTG_FS) RM0008 28.12.2 Host Tx FIFOs The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB.
Page 823: Host Mode
RM0008 USB on-the-go full-speed (OTG_FS) Transmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint. Note: More space allocated in the transmit IN Endpoint FIFO results in better performance on the USB.
Page 824: Otg_Fs Interrupts
USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS to fill in the available RAM space at best regardless of the current USB sequence. With these features: ● The application gains good margins to calibrate its intervention in order to optimize the CPU bandwidth usage: –...
Page 825: Figure 309. Interrupt Hierarchy
RM0008 USB on-the-go full-speed (OTG_FS) Figure 309. Interrupt hierarchy Interrupt Global interrupt mask (Bit 0) AHB configuration register 22 21 31 30 29 28 27 26 25 24 23 20 19 18 17:10 2 1 0 Core interrupt mask Core interrupt register register interrupt...
Page 826: Otg_Fs Control And Status Registers
USB on-the-go full-speed (OTG_FS) RM0008 28.16 OTG_FS control and status registers By reading from and writing to the control and status registers (CSRs) through the AHB slave interface, the application controls the OTG_FS controller. These registers are 32 bits wide, and the addresses are 32-bit block aligned. CSRs are classified as follows: ●...
Page 827: Csr Memory Map
RM0008 USB on-the-go full-speed (OTG_FS) 28.16.1 CSR memory map The host and device mode registers occupy different addresses. All registers are implemented in the AHB clock domain. Figure 310. CSR memory map 0000h Core global CSRs (1 Kbyte) 0400h Host mode CSRs (1 Kbyte) 0800h Device mode CSRs (1.5 Kbyte) 0E00h...
Page 828: Table 199. Host-Mode Control And Status Registers (Csrs)
USB on-the-go full-speed (OTG_FS) RM0008 Table 198. Core global control and status registers (CSRs) (continued) Address Acronym Register name offset OTG_FS_GINTSTS 0x014 OTG_FS core interrupt register (OTG_FS_GINTSTS) on page 840 OTG_FS_GINTMSK 0x018 OTG_FS interrupt mask register (OTG_FS_GINTMSK) on page 844 OTG_FS_GRXSTSR 0x01C OTG_FS Receive status debug read/OTG status read and pop registers...
Page 829: Table 200. Device-Mode Control And Status Registers
RM0008 USB on-the-go full-speed (OTG_FS) Table 199. Host-mode control and status registers (CSRs) (continued) Offset Acronym Register name address OTG_FS Host port control and status register (OTG_FS_HPRT) on OTG_FS_HPRT 0x440 page 856 0x500 0x520 OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) OTG_FS_HCCHARx (x = 0..7, where x = Channel_number) on page 859 0x6E0h...
Page 830 USB on-the-go full-speed (OTG_FS) RM0008 Table 200. Device-mode control and status registers (continued) Offset Acronym Register name address 0x920 0x940 OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, OTG_FS_DIEPCTLx where x = Endpoint_number) on page 872 0xAE0 OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) OTG_FS_DIEPINTx 0x908 (x = 0..3, where x = Endpoint_number) on page 879...
Page 831: Otg_Fs Global Registers
RM0008 USB on-the-go full-speed (OTG_FS) Table 201. Data FIFO (DFIFO) access register map FIFO access register section Address range Access Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access 0x1000–0x1FFC Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access 0x2000–0x2FFC Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access...
Page 832 USB on-the-go full-speed (OTG_FS) RM0008 Bit 19 BSVLD: B-session valid Indicates the device mode transceiver status. 0: B-session is not valid. 1: B-session is valid. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: Only accessible in device mode.
Page 833 RM0008 USB on-the-go full-speed (OTG_FS) Bit 8 HNGSCS: Host negotiation success The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPRQ) bit in this register is set. 0: Host negotiation failure 1: Host negotiation success Note: Only accessible in device mode.
Page 834 USB on-the-go full-speed (OTG_FS) RM0008 Bit 18 ADTOCHG: A-device timeout change The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. Note: Accessible in both device and host modes. Bit 17 HNGDET: Host negotiation detected The core sets this bit when it detects a host negotiation request on the USB.
Page 835 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS AHB configuration register (OTG_FS_GAHBCFG) Address offset: 0x008 Reset value: 0x0000 0000 This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming.
Page 836 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS USB configuration register (OTG_FS_GUSBCFG) Address offset: 0x00C Reset value: 0x0000 0A00 This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB.
Page 837 RM0008 USB on-the-go full-speed (OTG_FS) Bit 8 SRPCAP: SRP-capable The application uses this bit to control the OTG_FS controller’s SRP capabilities. If the core operates as a non-SRP-capable B-device, it cannot request the connected A-device (host) to activate V and start a session. 0: SRP capability is not enabled.
Page 838 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS reset register (OTG_FS_GRSTCTL) Address offset: 0x10 Reset value: 0x2000 0000 The application uses this register to reset various hardware features inside the core. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TXFNUM Reserved Bit 31 AHBIDL: AHB master idle...
Page 839 RM0008 USB on-the-go full-speed (OTG_FS) Bit 3 Reserved Bit 2 FCRST: Host frame counter reset The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. Note: Only accessible in host mode.
Page 840 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS core interrupt register (OTG_FS_GINTSTS) Address offset: 0x014 Reset value: 0x0400 0020 This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only.
Page 841 RM0008 USB on-the-go full-speed (OTG_FS) Bit 25 HCINT: Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_FS_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_FS_HCINTx register to determine the exact cause of the interrupt.
Page 842 USB on-the-go full-speed (OTG_FS) RM0008 Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint.
Page 843 RM0008 USB on-the-go full-speed (OTG_FS) Bit 3 SOF: Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB.
Page 844 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS interrupt mask register (OTG_FS_GINTMSK) Address offset: 0x018 Reset value: 0x0000 0000 This register works with the Core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the Core Interrupt (OTG_FS_GINTSTS) register bit corresponding to that interrupt is still set.
Page 845 RM0008 USB on-the-go full-speed (OTG_FS) Bits 23:22 Reserved Bit 21 IPXFRM: Incomplete periodic transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. IISOOXFRM: Incomplete isochronous OUT transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 20 IISOIXFRM: Incomplete isochronous IN transfer mask 0: Masked interrupt 1: Unmasked interrupt...
Page 846 USB on-the-go full-speed (OTG_FS) RM0008 Bit 11 USBSUSPM: USB suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 10 ESUSPM: Early suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bits 9:8 Reserved.
Page 847 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) Address offset for Read: 0x01C Address offset for Pop: 0x020 Reset value: 0x0000 0000 A read to the Receive status debug read register returns the contents of the top of the Receive FIFO.
Page 848 USB on-the-go full-speed (OTG_FS) RM0008 Device mode: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FRMNUM PKTSTS DPID BCNT EPNUM Reserved Bits 31:25 Reserved Bits 24:21 FRMNUM: Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB.
Page 849 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0) Address offset: 0x028 Reset value: 0x0000 0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NPTXFD/TX0FD NPTXFSA/TX0FSA r/rw...
Page 850 USB on-the-go full-speed (OTG_FS) RM0008 Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Bits [30:27]: Channel/endpoint number Bits [26:25]: – 00: IN/OUT token –...
Page 851 RM0008 USB on-the-go full-speed (OTG_FS) Bit 17 Reserved Bit 16 PWRDWN: Power down Used to activate the transceiver in transmission/reception 0: Power down active 1: Power down deactivated (“Transceiver active”) Bits 15:0 Reserved. OTG_FS core ID register (OTG_FS_CID) Address offset: 0x03C Reset value:0x00001000 This is a read only register containing the Product ID.
Page 852: Host-Mode Registers
USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) Address offset: 0x104 + (FIFO_number – 1) × 0x04 Reset value: 0x02000400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INEPTXFD INEPTXSA Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth...
Page 853 RM0008 USB on-the-go full-speed (OTG_FS) Bits 1:0 FSLSPCS: FS/LS PHY clock select When the core is in FS host mode 01: PHY clock is running at 48 MHz Others: Reserved When the core is in LS host mode 00: Reserved 01: Select 48 MHz PHY clock frequency 10: Select 6 MHz PHY clock frequency 11: Reserved...
Page 854 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM) Address offset: 0x408 Reset value: 0x0000 3FFF This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FTREM FRNUM...
Page 855 RM0008 USB on-the-go full-speed (OTG_FS) Bits 23:16 PTXQSAV: Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. 00: Periodic transmit request queue is full 01: dx1 location available 10: dx2 locations available bxn: dxn locations available (0 ≤...
Page 856 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK) Address offset: 0x418 Reset value: 0x0000 0000 The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
Page 857 RM0008 USB on-the-go full-speed (OTG_FS) Bits 16:13 PTCTL: Port test control The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. 0000: Test mode disabled 0001: Test_J mode 0010: Test_K mode 0011: Test_SE0_NAK mode...
Page 858 USB on-the-go full-speed (OTG_FS) RM0008 Bit 6 PRES: Port resume The application sets this bit to drive resume signaling on the port. The core continues to drive the resume signal until the application clears this bit. If the core detects a USB remote wakeup sequence, as indicated by the Port resume/remote wakeup detected interrupt bit of the Core interrupt register (WKUINT bit in OTG_FS_GINTSTS), the core starts driving resume signaling without application intervention and clears this bit when it detects a disconnect condition.
Page 859 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number) Address offset: 0x500 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MCNT EPNUM MPSIZ...
Page 860 USB on-the-go full-speed (OTG_FS) RM0008 Bit 15 EPDIR: Endpoint direction Indicates whether the transaction is IN or OUT. 0: OUT 1: IN Bits 14:11 EPNUM: Endpoint number Indicates the endpoint number on the device serving as the data source or sink. Bits 10:0 MPSIZ: Maximum packet size Indicates the maximum packet size of the associated endpoint.
Page 861 RM0008 USB on-the-go full-speed (OTG_FS) Bit 2 Reserved Bit 1 CHH: Channel halted Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. Bit 0 XFRC: Transfer completed Transfer completed normally without any errors. OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx) (x = 0..7, where x = Channel_number) Address offset: 0x50C + (Channel_number ×...
Page 862 USB on-the-go full-speed (OTG_FS) RM0008 Bit 2 Reserved Bit 1 CHHM: Channel halted mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed mask 0: Masked interrupt 1: Unmasked interrupt OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number) Address offset: 0x510 + (Channel_number ×...
Page 863: Device-Mode Registers
RM0008 USB on-the-go full-speed (OTG_FS) 28.16.4 Device-mode registers OTG_FS device configuration register (OTG_FS_DCFG) Address offset: 0x800 Reset value: 0x0220 0000 This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw...
Page 864 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device control register (OTG_FS_DCTL) Address offset: 0x804 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw Bits 31:12 Reserved...
Page 865: Table 203. Minimum Duration For Soft Disconnect
RM0008 USB on-the-go full-speed (OTG_FS) Bit 2 GINSTS: Global IN NAK status 0: A handshake is sent out based on the data availability in the transmit FIFO. 1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
Page 866 USB on-the-go full-speed (OTG_FS) RM0008 Bit 3 EERR: Erratic error The core sets this bit to report any erratic errors. Due to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_FS_GINTSTS register (ESUSP bit in OTG_FS_GINTSTS).
Page 867 RM0008 USB on-the-go full-speed (OTG_FS) Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints) 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask 0: Masked interrupt 1: Unmasked interrupt OTG_FS device OUT endpoint common interrupt mask register...
Page 868 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) Address offset: 0x818 Reset value: 0x0000 0000 When a significant event occurs on an endpoint, a OTG_FS_DAINT register interrupts the application using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit of the OTG_FS_GINTSTS register (OEPINT or IEPINT in OTG_FS_GINTSTS, respectively).
Page 869 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) Address offset: 0x81C Reset value: 0x0000 0000 The OTG_FS_DAINTMSK register works with the Device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_FS_DAINT register bit corresponding to that interrupt is still set.
Page 870 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device V pulsing time register (OTG_FS_DVBUSPULSE) Address offset: 0x082C Reset value: 0x0000 05B8 This register specifies the V pulsing time during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DVBUSP Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 871 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) Address offset: 0x900 Reset value: 0x0000 0000 This section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TXFNUM EPTYP MPSIZ...
Page 872 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status 1: The core is transmitting NAK handshakes on this endpoint. When this bit is set, either by the application or core, the core stops transmitting data, even if there are data available in the TxFIFO.
Page 873 RM0008 USB on-the-go full-speed (OTG_FS) Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt.
Page 874 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status It indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the TxFIFO.
Page 875 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0) Address offset: 0xB00 Reset value: 0x0000 8000 This section describes the OTG_FS_DOEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EPTYP MPSIZ Reserved...
Page 876 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there is space in the RxFIFO to accommodate the incoming packet.
Page 877 RM0008 USB on-the-go full-speed (OTG_FS) Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt.
Page 878 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
Page 879 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number) Address offset: 0x908 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events.
Page 880 USB on-the-go full-speed (OTG_FS) RM0008 Bit 0 XFRC: Transfer completed interrupt This field indicates that the programmed transfer is complete on the AHB as well as on the USB, for this endpoint. OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number) Address offset: 0xB08 + (Endpoint_number ×...
Page 881 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0) Address offset: 0x910 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (EPENA in OTG_FS_DIEPCTL0), the core modifies this register.
Page 882 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0) Address offset: 0xB10 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the Endpoint enable bit in the OTG_FS_DOEPCTL0 registers (EPENA bit in OTG_FS_DOEPCTL0), the core modifies this register.
Page 883 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number) Address offset: 0x910 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the Endpoint enable bit in the OTG_FS_DIEPCTLx registers (EPENA bit in OTG_FS_DIEPCTLx), the core modifies this register.
Page 884 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) Address offset for IN endpoints: 0x918 + (Endpoint_number × 0x20) This read-only register contains the free space information for the Device IN endpoint TxFIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INEPTFSAV Reserved...
Page 885: Otg_Fs Power And Clock Gating Control Register
RM0008 USB on-the-go full-speed (OTG_FS) STUPCNT: SETUP packet count Applies to control OUT Endpoints only. This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bit 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint.
Page 886: Otg_Fs Register Map
USB on-the-go full-speed (OTG_FS) RM0008 28.16.6 OTG_FS register map The table below gives the USB OTG register map and reset values. Table 204. OTG_FS register map and reset values Offset Register OTG_FS_GOT GCTL 0x000 Reserved Reserved Reserved Reset value OTG_FS_GOT GINT 0x004 Reserved...
Page 887 RM0008 USB on-the-go full-speed (OTG_FS) Table 204. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HNPT XFSIZ/ NPTXFD/TX0FD NPTXFSA/TX0FSA OTG_FS_DIEP 0x028 TXF0 Reset value OTG_FS_HNPT NPTXQTOP NPTQXSAV NPTXFSAV XSTS 0x02C Reset value OTG_FS_ GCCFG 0x038 Reserved Reserved Reset value OTG_FS_CID PRODUCT_ID 0x03C...
Page 888 USB on-the-go full-speed (OTG_FS) RM0008 Table 204. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCC MCNT EPNUM MPSIZ HAR3 0x560 Reset value OTG_FS_HCC MCNT EPNUM MPSIZ HAR4 0x580 Reset value OTG_FS_HCC MCNT EPNUM MPSIZ HAR5 0x5A0 Reset value OTG_FS_HCC MCNT EPNUM...
Page 889 RM0008 USB on-the-go full-speed (OTG_FS) Table 204. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCIN TMSK2 0x54C Reserved Reset value OTG_FS_HCIN TMSK3 0x56C Reserved Reset value OTG_FS_HCIN TMSK4 0x58C Reserved Reset value OTG_FS_HCIN 0x5AC TMSK5 Reserved Reset value OTG_FS_HCIN TMSK6 0x5CC...
Page 890 USB on-the-go full-speed (OTG_FS) RM0008 Table 204. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DCTL 0x804 Reserved Reset value OTG_FS_DSTS FNSOF 0x808 Reserved Reserved Reset value OTG_FS_DIEP 0x810 Reserved Reset value OTG_FS_DOEP 0x814 Reserved Reset value OTG_FS_DAIN OEPINT IEPINT 0x818 Reset value...
Page 891 RM0008 USB on-the-go full-speed (OTG_FS) Table 204. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEP TXFNUM MPSIZ CTL3 0x960 Reserved Reset value TG_FS_DTXFS INEPTFSAV 0x978 Reserved Reset value OTG_FS_DOEP EPTY MPSI CTL0 0xB00 Reserved Reserved Reset value OTG_FS_DOEP MPSIZ CTL1 0xB20...
Page 892: Otg_Fs Programming Model
USB on-the-go full-speed (OTG_FS) RM0008 Table 204. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DOEP INT2 0xB48 Reserved Reset value OTG_FS_DOEP INT3 0xB68 Reserved Reset value OTG_FS_DIEP PKTC XFRSIZ TSIZ0 0x910 Reserved Reserved Reset value OTG_FS_DIEP MCNT PKTCNT XFRSIZ TSIZ1 0x930...
Page 893 RM0008 USB on-the-go full-speed (OTG_FS) This section explains the initialization of the OTG_FS controller after power-on. The application must follow the initialization sequence irrespective of host or device mode operation. All core global registers are initialized according to the core’s configuration: Program the following fields in the OTG_FS_GAHBCFG register: –...
Page 894: Host Initialization
USB on-the-go full-speed (OTG_FS) RM0008 28.17.2 Host initialization To initialize the core as host, the application must perform the following steps: Program the HPRTINT in the OTG_FS_GINTMSK register to unmask Program the OTG_FS_HCFG register to select full-speed host Program the PPWR bit in OTG_FS_HPRT to 1. This drives V on the USB.
Page 895: Host Programming Model
RM0008 USB on-the-go full-speed (OTG_FS) register to determine the enumeration speed and perform the steps listed in Endpoint initialization on enumeration completion on page 912. At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0.
Page 896: Figure 311. Transmit Fifo Write Task
USB on-the-go full-speed (OTG_FS) RM0008 When an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received for an IN or OUT channel. The application must be able to receive other interrupts (DTERR, Nak, Data, TXERR) for the same channel before receiving the halt. When a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received.
Page 897: Figure 312. Receive Fifo Read Task
RM0008 USB on-the-go full-speed (OTG_FS) ● Reading the receive FIFO The application must ignore all packet statuses other than IN data packet (bx0010). Figure 312. Receive FIFO read task Start RXFLVL interrupt ? Unmask RXFLVL Mask RXFLVL Unmask RXFLVL interrupt interrupt interrupt Read the received...
Page 898 USB on-the-go full-speed (OTG_FS) RM0008 SETUP transaction operates in the same way but has only one packet. The assumptions are: – The application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). – The non-periodic transmit FIFO can hold two packets (128 bytes for FS). –...
Page 899: Figure 313. Normal Bulk/Control Out/Setup And Bulk/Control In Transactions
RM0008 USB on-the-go full-speed (OTG_FS) Figure 313. Normal bulk/control OUT/SETUP and bulk/control IN transactions Application Host Device init_reg(ch _1) Non-Periodic Request init _reg(ch_2) Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set _ch_en (ch _2) ch_1 write_tx_fifo (ch_1) ch_2 set _ch_en...
Page 900 USB on-the-go full-speed (OTG_FS) RM0008 De-allocate Channel else if (STALL) Transfer Done = 1 Unmask CHH Disable Channel else if (NAK or TXERR ) Rewind Buffer Pointers Unmask CHH Disable Channel if (TXERR) Increment Error Count Unmask ACK else Reset Error Count else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3))
Page 901 RM0008 USB on-the-go full-speed (OTG_FS) Reset Error Count Mask ACK else if (TXERR or BBERR or STALL) Unmask CHH Disable Channel if (TXERR) Increment Error Count Unmask ACK else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel...
Page 902: Figure 314. Bulk/Control In Transactions
USB on-the-go full-speed (OTG_FS) RM0008 Figure 314. Bulk/control IN transactions Application Host Device init_reg(ch _1) Non-Periodic Request init _reg(ch_2) Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set _ch_en (ch _2) ch_1 write_tx_fifo ch_2 (ch_1) set _ch_en ch_1 (ch _2) ch_2...
Page 903 RM0008 USB on-the-go full-speed (OTG_FS) The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO. The application must read and ignore the receive packet status when the receive packet status is not an IN data packet (PKTSTS in GRXSTSR ≠ 0b0010). The core generates the XFRC interrupt as soon as the receive packet status is read.
Page 904: Figure 315. Normal Interrupt Out/In Transactions
USB on-the-go full-speed (OTG_FS) RM0008 Figure 315. Normal interrupt OUT/IN transactions Application Host Device init _reg(ch_1) init_reg(ch _2) Periodic Request Queue Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en ch_1 (ch_2) ch_2 (micro) frame init _reg(ch_1) write_tx_fifo (ch_1) RXFLVL interrupt read_rx_sts...
Page 905 RM0008 USB on-the-go full-speed (OTG_FS) Disable Channel if (STALL) Transfer Done = 1 else if (NAK or TXERR) Rewind Buffer Pointers Reset Error Count Mask ACK Unmask CHH Disable Channel else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 Frame)
Page 906 USB on-the-go full-speed (OTG_FS) RM0008 else if (STALL or FRMOR or NAK or DTERR or BBERR) Mask ACK Unmask CHH Disable Channel if (STALL or BBERR) Reset Error Count Transfer Done = 1 else if (!FRMOR) Reset Error Count else if (TXERR) Increment Error Count Unmask ACK...
Page 907 RM0008 USB on-the-go full-speed (OTG_FS) ● Interrupt IN transactions The assumptions are: – The application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd (transfer size = 1 024 bytes). – The receive FIFO can hold at least one maximum-packet-size packet and two status Words per packet (1 031 bytes).
Page 908 USB on-the-go full-speed (OTG_FS) RM0008 ● Isochronous OUT transactions A typical isochronous OUT operation is shown in Figure 316. The assumptions are: – The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1 024 bytes). –...
Page 909: Figure 316. Normal Isochronous Out/In Transactions
RM0008 USB on-the-go full-speed (OTG_FS) Figure 316. Normal isochronous OUT/IN transactions Host Device Application init _reg(ch_1) init_reg(ch _2) Periodic Request Queue Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en ch_1 (ch_2) ch_2 (micro) frame init _reg(ch_1) write_tx_fifo (ch_1) RXFLVL interrupt read_rx_sts...
Page 910 USB on-the-go full-speed (OTG_FS) RM0008 else if (CHH) Mask CHH De-allocate Channel Code sample: Isochronous IN Unmask (TXERR/XFRC/FRMOR/BBERR) if (XFRC or FRMOR) if (XFRC and (OTG_FS_HCTSIZx.PKTCNT == 0)) Reset Error Count De-allocate Channel else Unmask CHH Disable Channel else if (TXERR or BBERR) Increment Error Count Unmask CHH Disable Channel...
Page 911 RM0008 USB on-the-go full-speed (OTG_FS) ● Isochronous IN transactions The assumptions are: – The application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame (transfer size = 1 024 bytes). –...
Page 912: Device Programming Model
USB on-the-go full-speed (OTG_FS) RM0008 the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of frame 2, which is very close to SOF). When OTG_FS controller detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP).
Page 913 RM0008 USB on-the-go full-speed (OTG_FS) At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0. Endpoint initialization on SetAddress command This section describes what the application must do when it receives a SetAddress command in a SETUP packet.
Page 914: Operational Model
USB on-the-go full-speed (OTG_FS) RM0008 In the endpoint to be deactivated, clear the USB active endpoint bit in the OTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the OTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints). Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, which results in a timeout on the USB.
Page 915: Figure 317. Receive Fifo Packet Read
RM0008 USB on-the-go full-speed (OTG_FS) completed. After this entry is popped from the receive FIFO, the core asserts a Transfer Completed interrupt on the specified OUT endpoint. After the data payload is popped from the receive FIFO, the RXFLVL interrupt (OTG_FS_GINTSTS) must be unmasked.
Page 916 USB on-the-go full-speed (OTG_FS) RM0008 determine the correct number of SETUP packets received in the Setup stage of a control transfer. – STUPCNT = 3 in OTG_FS_DOEPTSIZx The application must always allocate some extra space in the Receive data FIFO, to be able to receive up to three SETUP packets on a control endpoint.
Page 917: Figure 318. Processing A Setup Packet
RM0008 USB on-the-go full-speed (OTG_FS) Figure 318. Processing a SETUP packet Wait for STUP in OTG_FS_DOEPINTx rem_supcnt = rd_reg(DOEPTSIZx) setup_cmd[31:0] = mem[4 – 2 * rem_supcnt] setup_cmd[63:32] = mem[5 – 2 * rem_supcnt] Find setup cmd type Read ctrl-rd/wr/2 stage Write 2-stage setup_np_in_pkt...
Page 918 USB on-the-go full-speed (OTG_FS) RM0008 To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field: – SGONAK = 1 in OTG_FS_DCTL Wait for the assertion of the GONAKEFF interrupt in OTG_FS_GINTSTS. When asserted, this interrupt indicates that the core has stopped receiving any type of data except SETUP packets.
Page 919 RM0008 USB on-the-go full-speed (OTG_FS) Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer. For OUT transfers, the transfer size field in the endpoint’s transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the Word boundary.
Page 920 USB on-the-go full-speed (OTG_FS) RM0008 The OUT data transfer completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions: – The transfer size is 0 and the packet count is 0 – The last OUT data packet written to the receive FIFO is a short packet (0 ≤...
Page 921 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS_DOEPTSIZx with the data PID of the last isochronous OUT data packet read from the receive FIFO. Application programming sequence: Program the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding packet count Program the OTG_FS_DOEPCTLx register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits.
Page 922 USB on-the-go full-speed (OTG_FS) RM0008 (IISOOXFRM in OTG_FS_GINTSTS), indicating that an XFRC interrupt (in OTG_FS_DOEPINTx) is not asserted on at least one of the isochronous OUT endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the USB. Application programming sequence: Asserting the IISOOXFRM interrupt (OTG_FS_GINTSTS) indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer.
Page 923: Figure 319. Bulk Out Transaction
RM0008 USB on-the-go full-speed (OTG_FS) Examples This section describes and depicts some fundamental transfer types and scenarios. ● Bulk OUT transaction Figure 319 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB and describes the events involved in the process. Figure 319.
Page 924 USB on-the-go full-speed (OTG_FS) RM0008 IN data transfers ● Packet write This section describes how the application writes data packets to the endpoint FIFO when dedicated transmit FIFOs are enabled. The application can either choose the polling or the interrupt mode. –...
Page 925 RM0008 USB on-the-go full-speed (OTG_FS) To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed. – SNAK = 1 in OTG_FS_DIEPCTLx Wait for assertion of the INEPNE interrupt in OTG_FS_DIEPINTx. This interrupt indicates that the core has stopped transmitting data on the endpoint.
Page 926 USB on-the-go full-speed (OTG_FS) RM0008 ● Generic non-periodic IN data transfers Application requirements: Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer are part of a single buffer. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet.
Page 927 RM0008 USB on-the-go full-speed (OTG_FS) handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the packet count field.
Page 928 USB on-the-go full-speed (OTG_FS) RM0008 The application can only schedule data transfers one frame at a time. (MCNT – 1) × MPSIZ ≤ XFERSIZ ≤ MCNT × MPSIZ – – PKTCNT = MCNT (in OTG_FS_DIEPTSIZx) – If XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short packet.
Page 929 RM0008 USB on-the-go full-speed (OTG_FS) Application programming sequence: Program the OTG_FS_DIEPCTLx register with the endpoint characteristics and set the CNAK and EPENA bits. Write the data to be transmitted in the next frame to the transmit FIFO. Asserting the ITTXFE interrupt (in OTG_FS_DIEPINTx) indicates that the application has not yet written all data to be transmitted to the transmit FIFO.
Page 930 USB on-the-go full-speed (OTG_FS) RM0008 Application programming sequence: The application can ignore the IN token received when TxFIFO empty interrupt in OTG_FS_DIEPINTx on any isochronous IN endpoint, as it eventually results in an incomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS). Assertion of the incomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS) indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints.
Page 931: Worst Case Response Time
RM0008 USB on-the-go full-speed (OTG_FS) application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt. 28.17.7 Worst case response time When the OTG_FS controller acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT.
Page 932: Otg Programming Model
USB on-the-go full-speed (OTG_FS) RM0008 Figure 320. TRDT max timing case 50ns 100ns 150ns 200ns HCLK PCLK tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr spr_rdata srcbuf_push srcbuf_rdata 5 Clocks ai15680 28.17.8 OTG programming model The OTG_FS controller is an OTG device supporting HNP and SRP. When the core is connected to an “A”...
Page 933: Figure 321. A-Device Srp
RM0008 USB on-the-go full-speed (OTG_FS) Figure 321. A-device SRP Suspend DRV_VBUS VBUS_VALID pulsing A_VALID Connect Data line pulsing ai15681 1. DRV_VBUS = V drive signal to the PHY VBUS_VALID = V valid signal from PHY A_VALID = A-peripheral V level signal to PHY D+ = Data plus line D- = Data minus line To save power, the application suspends and turns off port power when the bus is idle...
Page 934: Figure 322. B-Device Srp
USB on-the-go full-speed (OTG_FS) RM0008 Figure 322. B-device SRP Suspend VBUS_VALID B_VALID DISCHRG_VBUS SESS_END Data line pulsing Connect pulsing CHRG_VBUS ai15682 1. VBUS_VALID = V valid signal from PHY B_VALID = B-peripheral valid session to PHY DISCHRG_VBUS = discharge signal to PHY SESS_END = session end signal to PHY CHRG_VBUS = charge V signal to PHY...
Page 935: Figure 323. A-Device Hnp
RM0008 USB on-the-go full-speed (OTG_FS) A-device host negotiation protocol HNP switches the USB host role from the A-device to the B-device. The application must set the HNP-capable bit in the Core USB configuration register to enable the OTG_FS controller to perform HNP as an A-device. Figure 323.
Page 936: Figure 324. B-Device Hnp
USB on-the-go full-speed (OTG_FS) RM0008 In Negotiated mode, the OTG_FS controller detects the suspend, disconnects, and switches back to the host role. The OTG_FS controller asserts the DM pull down and DM pull down in the PHY to indicate its assumption of the host role. The OTG_FS controller sets the Connector ID status change interrupt in the OTG Interrupt Status register.
Page 937 RM0008 USB on-the-go full-speed (OTG_FS) The A-device responds by activating its OTG_FS_DP pull-up resistor within 3 ms of detecting SE0. The OTG_FS controller detects this as a connect. The OTG_FS controller sets the host negotiation success status change interrupt in the OTG Interrupt status register, indicating the HNP status.
Page 938: Ethernet (Eth): Media Access Control (Mac) With Dma Controller
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes. XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Page 939: Mac Core Features
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller 29.2.1 MAC core features ● Supports 10/100 Mbit/s data transfer rates with external PHY interfaces ● IEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet ● Supports both full-duplex and half-duplex operations –...
Page 940: Dma Features
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 ● Option to filter all error frames on reception and not forward them to the application in Store-and-Forward mode ● Option to forward under-sized good frames ● Supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the Receive FIFO ●...
Page 941: Ethernet Pins
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller 29.3 Ethernet pins Table 205 shows the MAC signals and the corresponding MII/RMII default or remapped signals. It also indicates the pins onto which the signals are input or output, and the pin configuration.
Page 942: Ethernet Functional Description: Smi, Mii And Rmii
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Table 205. Ethernet pin configuration (continued) MAC signals MII default MII remap RMII default RMII remap Pin configuration ETH_MII_RXD2 RXD2 PD11 Floating input (reset state) ETH_MII_RXD3 RXD3 PD12 Floating input (reset state) 29.4 Ethernet functional description: SMI, MII and RMII The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated...
Page 943: Table 206. Management Frame Format
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The application can select one of the 32 PHYs and one of the 32 registers within any PHY and send control data or receive status information. Only one register in one PHY can be addressed at any given time.
Page 944: Figure 327. Mdio Timing And Frame Structure - Write Cycle
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 drives high-impedance on the MDIO line for the 2 bits of TA. The PHY device must drive a high-impedance state on the first bit of TA, a zero bit on the second one. For a write transaction, the MAC controller drives a <10>...
Page 945: Media-Independent Interface: Mii
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 328. MDIO timing and frame structure - Read cycle MDIO 32 1's 0 1 1 A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 D15 D14 D1 D0 Start Register address Turn Preamble...
Page 946: Figure 329. Media Independent Interface Signals
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 329. Media independent interface signals TX _CLK STM32 TXD[3:0] TX_ER TX_EN RX_CLK RXD[3:0] External RX_ER RX_DV MDIO ai15622 ● MII_TX_CLK: continuous clock that provides the timing reference for the TX data transfer.
Page 947: Table 208. Tx Interface Signal Encoding
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller that follows the final nibble. In order to receive the frame correctly, the MII_RX_DV signal must encompass the frame, starting no later than the SFD field. ● MII_RX_ER: receive error must be asserted for one or more clock periods (MII_RX_CLK) to indicate to the MAC sublayer that an error was detected somewhere in the frame.
Page 948: Reduced Media-Independent Interface: Rmii
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 330. MII clock sources STM32 External TX _CLK 25 MHz RX _CLK For 10/100 Mbit/s 25 MHz 25 MHz ai15623 29.4.3 Reduced media-independent interface: RMII The reduced media-independent interface (RMII) specification reduces the pin count between the STM32F100xx Ethernet peripheral and the external Ethernet in 10/100 Mbit/s.
Page 949: Mii/Rmii Selection
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller RMII clock sources As described in the RMII clock sources section, the STM32F107xx could provide this 50 MHz clock signal on its MCO output pin and you then have to configure this output value through PLL configuration.
Page 950: Ethernet Functional Description: Mac 802.3
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed on the same GPIO pin. 29.5 Ethernet functional description: MAC 802.3 The IEEE 802.3 International Standard for local area networks (LANs) employs the CSMA/CD (carrier sense multiple access with collision detection) as the access method.
Page 951: Figure 334. Address Field Format
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 335 Figure 336 describe the frame structure (untagged and tagged) that includes the following fields: ● Preamble: 7-byte field used for synchronization purposes (PLS circuitry) Hexadecimal value: 55-55-55-55-55-55-55 Bit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 (right-to-left bit transmission) ●...
Page 952 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 hexadecimal). This constant field is used to distinguish tagged and untagged MAC frames. – 2-byte field containing the Tag control information field subdivided as follows: a 3- bit user priority, a canonical format indicator (CFI) bit and a 12-bit VLAN Identifier. The length of the tagged MAC frame is extended by 4 bytes by the QTag Prefix.
Page 953: Figure 335. Mac Frame Format
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 335. MAC frame format 7 bytes Preamble 1 byte 6 bytes Destination address Bytes within frame transmitted 6 bytes Source address top to bottom 2 bytes MAC client length/type MAC client data 46-1500 bytes 4 bytes...
Page 954: Mac Frame Transmission
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 29.5.2 MAC frame transmission The DMA controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the FIFO by the DMA. The frames are then popped out and transferred to the MAC core.
Page 955 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The encoding is defined by the following polynomial. G x ( ) Transmit protocol The MAC controls the operation of Ethernet frame transmission. It performs the following functions to meet the IEEE 802.3/802.3z specifications.
Page 956 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 configured for 96 bit times, the MAC follows the rule of deference specified in Section 4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is detected during the first two-thirds (64-bit times for all IFG values) of the IFG interval.
Page 957 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller frame is being transmitted. As soon as the first frame has been transferred and the status is received from the MAC, it is pushed to the DMA. If the DMA has already completed sending the second packet to the FIFO, the second transmission must wait for the status of the first packet before proceeding to the next frame.
Page 958 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 You must make sure the Transmit FIFO is deep enough to store a complete frame before that frame is transferred to the MAC Core transmitter. If the FIFO depth is less than the input Ethernet frame size, the payload (TCP/UDP/ICMP) checksum insertion function is bypassed and only the frame’s IPv4 Header checksum is modified, even in Store-and-forward mode.
Page 959: Figure 337. Transmission Bit Order
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The checksum is calculated for the TCP, UDP, or ICMP payload and inserted into its corresponding field in the header. It can work in the following two modes: – In the first mode, the TCP, UDP, or ICMPv6 pseudo-header is not included in the checksum calculation and is assumed to be present in the input frame’s checksum field.
Page 960: Figure 338. Transmission With No Collision
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 MII/RMII transmit timing diagrams Figure 338. Transmission with no collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15631 Figure 339. Transmission with collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15651 Figure 340 shows a frame transmission in MII and RMII. 960/1096 Doc ID 13902 Rev 12...
Page 961: Mac Frame Reception
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 340. Frame transmission in MMI and RMII modes MII_RX_CLK MII_TX_EN MII_TXD[3:0] RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] ai15652 29.5.3 MAC frame reception The MAC received frames are pushes into the Rx FIFO. The status (fill level) of this FIFO is indicated to the DMA once it crosses the configured receive threshold (RTC in the ETH_DMAOMR register) so that the DMA can initiate pre-configured burst transfers towards the AHB interface.
Page 962 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 If the received frame length/type field is less than 0x600 and if the MAC is programmed for the auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to the count specified in the length/type field, then starts dropping bytes (including the FCS field).
Page 963: Table 210. Frame Statuses
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Table 210. Frame statuses Bit 18: Bit 27: Header Bit 28: Payload Frame status Ethernet frame checksum error checksum error The frame is an IEEE 802.3 frame (Length field value is less than 0x0600). IPv4/IPv6 Type frame in which no checksum error is detected.
Page 964 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Meanwhile, if another Pause frame is detected with a zero Pause time value, the MAC resets the Pause time and manages this new pause request. If the received control frame matches neither the type field (0x8808), the opcode (0x00001), nor the byte length (64 bytes), or if there is a CRC error, the MAC does not generate a Pause.
Page 965: Figure 341. Receive Bit Order
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 341. Receive bit order Di-bit stream MII_RXD[3:0] Nibble stream ai15633 Figure 342. Reception with no error MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15634 Figure 343. Reception with errors MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR...
Page 966: Mac Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 344. Reception with false carrier indication MII_RX_CLK MII_RX_DV MII_RXD[3:0] MII_RX_ERR ai15636 29.5.4 MAC interrupts Interrupts can be generated from the MAC core as a result of various events. The ETH_MACSR register describes the events that can cause an interrupt from the MAC core.
Page 967 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Unicast destination address filter The MAC supports up to 4 MAC addresses for unicast perfect filtering. If perfect filtering is selected (HU bit in the Frame filter register is reset), the MAC compares all 48 bits of the received unicast address with the programmed MAC address for any match.
Page 968: Table 211. Destination Address Filtering Table
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Broadcast address filter The MAC does not filter any broadcast frames in the default mode. However, if the MAC is programmed to reject all broadcast frames by setting the BFD bit in the Frame filter register, any broadcast frames are dropped.
Page 969: Mac Loopback Mode
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Table 211. Destination address filtering table (continued) Frame DAIF PAM DB DA filter operation type Pass all frames Pass all frames Pass on Perfect/Group filter match and drop PAUSE control frames if PCF = 0x Pass on hash filter match and drop PAUSE control frames if PCF = 0x Pass on hash or perfect/Group filter...
Page 970: Power Management: Pmt
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Section 29.8: Ethernet register descriptions describes the various counters and lists the addresses of each of the statistics counters. This address is used for read/write accesses to the desired transmit/receive counter. The Receive MMC counters are updated for frames that pass address filtering.
Page 971: Figure 346. Wakeup Frame Filter Register
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller wakeup frame filter register to reach the last register. Each read/write points the wakeup frame filter register to the next filter register. Figure 346. Wakeup frame filter register Filter 0 Byte Mask Wakeup frame filter reg0 Filter 1 Byte Mask Wakeup frame filter reg1...
Page 972 SRAM. To disable the Ethernet DMA, clear the ST bit and the SR bit (for the transmit DMA and the receive DMA, respectively) in the ETH_DMAOMR register.
Page 973: Precision Time Protocol (Ieee1588 Ptp)
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Disable the transmit DMA and wait for any previous frame transmissions to complete. These transmissions can be detected when the transmit interrupt ETH_DMASR register[0] is received. Disable the MAC transmitter and MAC receiver by clearing the RE and TE bits in the ETH_MACCR configuration register.
Page 974: Figure 347. Networked Time Synchronization
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 347. Networked time synchronization Master clock time Slave clock time Sync message Data at slave clock Follow_up message containing value of t1 Delay_Req message Delay_Resp message containing value of t4 time ai15669 The master broadcasts PTP Sync messages to all its nodes.
Page 975 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns. The generation, update and modification of the System Time are described in the Section : System Time correction methods.
Page 976: Figure 348. System Time Update Using The Fine Correction Method
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high- precision frequency multiplier or divider. Figure 348 shows this algorithm. Figure 348. System time update using the Fine correction method Addend register Addend update Accumulator register...
Page 977 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The algorithm is as follows: ● At time MasterSyncTime (n) the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTime (n) and computes MasterClockTime (n) as: MasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n) ●...
Page 978: Figure 349. Ptp Trigger Output To Tim2 Itr1 Connection
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Programming steps for system time update in the Coarse correction method To synchronize or update the system time in one process (coarse correction method), perform the following steps: Write the offset (positive or negative) in the Time stamp update high and low registers. Set bit 3 (TSSTU) in the Time stamp control register.
Page 979: Ethernet Functional Description: Dma Controller Operation
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller PTP pulse-per-second output signal This PTP pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and the master reference clock, both clocks were given a pulse-per-second (PPS) output signal that may be connected to an oscilloscope if necessary.
Page 980: Initialization Of A Transfer Using Dma
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 351. Descriptor ring and chain structure Ring structure Chain structure Buffer 1 Buffer 1 Descriptor 0 Descriptor 0 Buffer 2 Buffer 1 Descriptor 1 Buffer 2 Buffer 1 Descriptor 1 Buffer 1 Descriptor 2 Buffer 2...
Page 981: Host Data Buffer Alignment
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller INCR4, INCR8, INCR16 and SINGLE transactions. Otherwise (no fixed-length burst), it transfers data using INCR (undefined length) and SINGLE transactions. The Receive DMA initiates a data transfer only when sufficient data for the configured burst is available in Receive FIFO or when the end of frame (when it is less than the configured burst length) is detected in the Receive FIFO.
Page 982: Dma Arbiter
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet frame data. Once the ST bit (ETH_DMAOMR register[13]) is set, the DMA enters the Run state. While in the Run state, the DMA polls the transmit descriptor list for frames requiring transmission.
Page 983 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Unavailable (ETH_DMASR register[2]) and Normal Interrupt Summary (ETH_DMASR register[16]) bits are set. The transmit engine proceeds to Step 9. If the acquired descriptor is flagged as owned by DMA (TDES0[31] is set), the DMA decodes the transmit data buffer address from the acquired descriptor.
Page 984: Figure 352. Txdma Operation In Default Mode
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 352. TxDMA operation in Default mode Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll demand error? TxDMA suspended bit set? Transfer data from buffer(s) (AHB) error? Frame xfer complete? Close intermediate Wait for Tx status...
Page 985 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The DMA operates as described in steps 1–6 of the TxDMA (default mode). Without closing the previous frame’s last descriptor, the DMA fetches the next descriptor. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer address in this descriptor.
Page 986: Figure 353. Txdma Operation In Osf Mode
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 353. TxDMA operation in OSF mode Start TxDMA Stop TxDMA Start (Re-)fetch next descriptor (AHB) Poll error? demand TxDMA suspended bit set? Previous frame Transfer data from status available buffer(s) (AHB) Time stamp...
Page 987: Figure 354. Transmit Descriptor
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller indicates the last buffer of the frame. After the last buffer of the frame has been transmitted, the DMA writes back the final status information to the transmit descriptor 0 (TDES0) word of the descriptor that has the last segment set in transmit descriptor 0 (TDES0[29]).
Page 988 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 ● TDES0: Transmit descriptor Word0 The application software has to program the control bits [30:26]+[23:20] plus the OWN bit [31] during descriptor initialization. When the DMA updates the descriptor (or writes it back), it resets all the control bits plus the OWN bit, and reports only the status bits.
Page 989 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Bit 20 TCH: Second address chained When set, this bit indicates that the second address in the descriptor is the next descriptor address rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care”...
Page 990 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Bit 10 NC: No carrier When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during transmission. Bit 9 LCO: Late collision When set, this bit indicates that frame transmission was aborted due to a collision occurring after the collision window (64 byte times, including preamble, in MII mode).
Page 991: Rx Dma Configuration
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller ● TDES2: Transmit descriptor Word2 TDES2 contains the address pointer to the first buffer of the descriptor or it contains time stamp data. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TBAP1/TBAP/TTSL Bits 31:0 TBAP1: Transmit buffer 1 address pointer / Transmit frame time stamp low...
Page 992 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 The CPU sets up Receive descriptors (RDES0-RDES3) and sets the OWN bit (RDES0[31]). Once the SR (ETH_DMAOMR register[1]) bit is set, the DMA enters the Run state. While in the Run state, the DMA polls the receive descriptor list, attempting to acquire free descriptors.
Page 993: Figure 355. Receive Dma Operation
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 355. Receive DMA operation Start RxDMA Start Stop RxDMA (Re-)Fetch next Poll demand / descriptor new frame available (AHB) RxDMA suspended error? Frame transfer Own bit set? complete? Frame data Flush disabled ? available ? Flush the...
Page 994 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Receive descriptor acquisition The receive engine always attempts to acquire an extra descriptor in anticipation of an incoming frame. Descriptor acquisition is attempted if any of the following conditions is/are satisfied: ●...
Page 995: Figure 356. Rx Dma Descriptor Structure
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Rx DMA descriptors The descriptor structure consists of four 32-bit words (16 bytes). These are shown in Figure 356. The bit descriptions of RDES0, RDES1, RDES2 and RDES3 are given below. Figure 356.
Page 996 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Bit 15 ES: Error summary Indicates the logical OR of the following bits: – RDES0[1]: CRC error – RDES0[3]: Receive error – RDES0[4]: Watchdog timeout – RDES0[6]: Late collision – RDES0[7]: Giant frame (This is not applicable when RDES0[7] indicates an IPV4 header checksum error.) –...
Page 997: Table 213. Receive Descriptor 0
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Bit 3 RE: Receive error When set, this bit indicates that the RX_ERR signal is asserted while RX_DV is asserted during frame reception. Bit 2 DE: Dribble bit error When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles).
Page 998 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 ● RDES1: Receive descriptor Word1 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RBS2 RBS2 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit 31 DIC: Disable interrupt on completion...
Page 999 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller ● RDES2: Receive descriptor Word2 RDES2 contains the address pointer to the first data buffer in the descriptor, or it contains time stamp data. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RBP1 / RTSL rw rw rw rw rw rw rw...
Page 1000: Dma Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 ● RDES3: Receive descriptor Word3 RDES3 contains the address pointer either to the second data buffer in the descriptor or to the next descriptor, or it contains time stamp data. 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RBP2 / RTSH...

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Stm32f102xx Stm32f103xx Stm32f105xx Stm32f107xx