ST STM32F101 series Reference Manual page 550

RM0008
Bits 31:24 MEMHIZx: Common memory x databus HiZ time
Bits 23:16 MEMHOLDx: Common memory x hold time
Bits 15:8 MEMWAITx: Common memory x wait time
Bits 7:0 MEMSETx: Common memory x setup time
Attribute memory space timing registers 2..4 (FSMC_PATT2..4)
Address offset: 0xA000 0000 + 0x4C + 0x20 * (x – 1), x = 2..4
Reset value: 0xFCFC FCFC
Each FSMC_PATTx (x = 2..4) read/write register contains the timing information for PC
Card/CompactFlash or NAND Flash memory bank x. It is used for 8-bit accesses to the
attribute memory space of the PC Card/CompactFlash or to access the NAND Flash for the
last address write access if the timing must differ from that of previous accesses (for
Ready/Busy management, refer to
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
ATTHIZx
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Defines the number of HCLK (+1 only for NAND) clock cycles during which the databus is
kept in HiZ after the start of a PC Card/NAND Flash write access to common memory space
on socket x. Only valid for write transaction:
0000 0000: (0x00) 0 HCLK cycle (for PC Card)
1111 1111: (0xFF) 255 HCLK cycles (for PC Card) - (default value after reset)
Defines the number of HCLK clock cycles to hold address (and data for write access) after
the command deassertion (NWE, NOE), for PC Card/NAND Flash read or write access to
common memory space on socket x:
0000 0000: reserved
0000 0001: 1 HCLK cycle
1111 1111: 255 HCLK cycles (default value after reset)
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for PC Card/NAND Flash read or write access to common memory space on socket
x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low)
at the end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT)
(default value after reset)
Defines the number of HCLK (+1 for PC Card, +2 for NAND) clock cycles to set up the
address before the command assertion (NWE, NOE), for PC Card/NAND Flash read or write
access to common memory space on socket x:
0000 0000: 1 HCLK cycle (for PC Card) / HCLK cycles (for NAND Flash)
1111 1111: 256 HCLK cycles (for PC Card) / 257 HCLK cycles (for NAND Flash) - (default
value after reset)
ATTHOLDx
Flexible static memory controller (FSMC)
Section 21.6.5: NAND Flash pre-wait
ATTWAITx
DocID13902 Rev 15
functionality).
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ATTSETx
2 1 0
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