Figure 187. Mode1 Read Accesses; Figure 188. Mode1 Write Accesses - ST STM32F101 series Reference Manual

Flexible static memory controller (FSMC)
1. NBL[1:0] are driven low during read access.
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
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Figure 187. Mode1 read accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
D[15:0]

Figure 188. Mode1 write accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
DocID13902 Rev 15
Memory transaction
(ADDSET +1) (DATAST + 1)
HCLK cycles HCLK cycles
Memory transaction
(ADDSET +1)
HCLK cycles
data driven
by memory
2 HCLK
cycles
Data sampled Data strobe
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
RM0008
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