Figure 57. Counter Timing Diagram, Internal Clock Divided By 4; Figure 58. Counter Timing Diagram, Internal Clock Divided By N; Figure 59. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded) - ST STM32F101 series Reference Manual

RM0008
Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

Figure 57. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 58. Counter timing diagram, internal clock divided by N

CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
DocID13902 Rev 15
Advanced-control timers (TIM1&TIM8)
0035
1F
20
preloaded)
CEN
31 32 33 34 35 36
FF
0036 0000 0001
00
00 01 02 03 04 05 06 07
36
298/1128
359