Afio Registers; Event Control Register (Afio_Evcr) - ST STM32F101 series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.4

AFIO registers

Refer to
Note: To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock
should first be enabled. Refer to
(RCC_APB2ENR).
The peripheral registers have to be accessed by words (32-bit).
9.4.1

Event control register (AFIO_EVCR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
Bits 31:8 Reserved
Bit 7 EVOE: Event output enable
Bits 6:4 PORT[2:0]: Port selection
Note: The EVENTOUT signal output capability is not extended to ports PF and PG.
Bits 3:0 PIN[3:0]: Pin selection (x = A .. E)
183/1128
Section 2.1 on page 47for a list of abbreviations used in register descriptions.
28 27 26 25
12 11 10 9
Reserved
Set and cleared by software. When set the EVENTOUT Cortex
I/O selected by the PORT[2:0] and PIN[3:0] bits.
Set and cleared by software. Select the port used to output the Cortex
000: PA selected
001: PB selected
010: PC selected
011: PD selected
100: PE selected
Set and cleared by software. Select the pin used to output the Cortex
0000: Px0 selected
0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected
Section 7.3.7: APB2 peripheral clock enable register
24 23 22
Reserved
8 7 6
EVOE
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DocID13902 Rev 15
21 20 19
5 4 3
PORT[2:0]
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®
output is connected to the
®
EVENTOUT signal.
®
EVENTOUT signal.
RM0008
18 17 16
2 1 0
PIN[3:0]
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