Ethernet Functional Description: Smi, Mii And Rmii; Station Management Interface: Smi; Figure 326. Eth Block Diagram - ST STM32F101 series Reference Manual

RM0008
MAC signals
ETH_MII_RXD2
ETH_MII_RXD3
29.4

Ethernet functional description: SMI, MII and RMII

The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated
DMA controller. It supports both default media-independent interface (MII) and reduced
media-independent interface (RMII) through one selection bit (refer to AFIO_MAPR
register).
The DMA controller interfaces with the Core and memories through the AHB Master and
Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave
interface accesses Control and Status Registers (CSR) space.
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before
transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet
frames received from the line until they are transferred to system memory by the DMA.
The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of
configuration registers permit the user to select the desired mode and features for the MAC
and the DMA controller.
Note: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
1. For AHB connections please refer to
29.4.1

Station management interface: SMI

The station management interface (SMI) allows the application to access any PHY registers
through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.
Ethernet (ETH): media access control (MAC) with DMA controller
Table 208. Ethernet pin configuration (continued)
MII default MII remap RMII default RMII remap
- RXD2
- RXD3

Figure 326. ETH block diagram

DocID13902 Rev 15
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Figure 1: System architecture (low-, medium-, XL-density
Pin Pin configuration
PD11 Floating input (reset state)
PD12 Floating input (reset state)
devices).
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