Spi Status Register (Spi_Sr) - ST STM32F101 series Reference Manual

RM0008
Note: This bit is not used in I
Bit 1 TXDMAEN: Tx buffer DMA enable
Bit 0 RXDMAEN: Rx buffer DMA enable
25.5.3

SPI status register (SPI_SR)

Address offset: 0x08
Reset value: 0x0002
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BSY: Busy flag
Note: BSY flag must be used with caution: refer to
Bit 6 OVR: Overrun flag
Bit 5 MODF: Mode fault
Note: This bit is not used in I
Bit 4 CRCERR: CRC error flag
Note: This bit is not used in I
When this bit is set, the DMA request is made whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
When this bit is set, the DMA request is made whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled
12 11 10 9
Reserved
0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Section 25.3.8: Disabling the
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
page 731 for the software sequence.
0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
page 712 for the software sequence.
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
2
S mode
8 7 6
BSY OVR
r r
SPI.
2
S mode
2
S mode.
DocID13902 Rev 15
Serial peripheral interface (SPI)
5 4 3
CRC CHSID
MODF UDR
ERR
r rc_w0 r
Section 25.3.7: Status flags
Section 25.4.7 on
Section 25.3.10 on
2 1 0
TXE RXNE
E
r r r
and
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