Backup Domain Reset; Clocks - ST STM32F101 series Reference Manual

RM0008
7.1.3

Backup domain reset

The backup domain has two specific resets that affect only the backup domain (see
Figure 4).
A backup domain reset is generated when one of the following events occurs:
1. Software reset, triggered by setting the BDRST bit in the
register
2. V
DD
7.2

Clocks

Three different clock sources can be used to drive the system clock (SYSCLK):
•
HSI oscillator clock
•
HSE oscillator clock
•
PLL clock
The devices have the following two secondary clock sources:
•
40 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode.
•
32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Low-, medium-, high- and XL-density reset and clock control (RCC)
(RCC_BDCR).
or V power on, if both supplies have previously been powered off.
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