Csr Memory Map - ST STM32F101 series Reference Manual

USB on-the-go full-speed (OTG_FS)
CSRs are classified as follows:
•
Core global registers
•
Host-mode registers
•
Host global registers
•
Host port CSRs
•
Host channel-specific registers
•
Device-mode registers
•
Device global registers
•
Device endpoint-specific registers
• Power and clock-gating registers
•
Data FIFO (DFIFO) access registers
Only the Core global, Power and clock-gating, Data FIFO access, and host port control and
status registers can be accessed in both host and device modes. When the OTG_FS
controller is operating in one mode, either device or host, the application must not access
registers from the other mode. If an illegal access occurs, a mode mismatch interrupt is
generated and reflected in the Core interrupt register (MMIS bit in the OTG_FS_GINTSTS
register). When the core switches from one mode to the other, the registers in the new mode
of operation must be reprogrammed as they would be after a power-on reset.
28.16.1

CSR memory map

The host and device mode registers occupy different addresses. All registers are
implemented in the AHB clock domain.
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