ST STM32F101xx series Programming Manual
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ST STM32F101xx series Programming Manual

ST STM32F101xx series Programming Manual

Stm32f10xxx flash memory microcontrollers
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PM0075
Programming manual
STM32F10xxx Flash memory microcontrollers
Introduction
This programming manual describes how to program the Flash memory of STM32F101xx,
STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx microcontrollers. For
convenience, these will be referred to as STM32F10xxx in the rest of this document unless
otherwise specified.
The STM32F10xxx embedded Flash memory can be programmed using in-circuit
programming or in-application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the boot loader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
2
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I
C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the
Flash memory while the application is running. Nevertheless, part of the application has to
have been previously programmed in the Flash memory using ICP.
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a prefetch buffer that speeds up CPU code execution. It also
implements the logic necessary to carry out Flash memory operations (Program/Erase).
Program/Erase operations can be performed over the whole product voltage range.
Read/Write protections and option bytes are also implemented.
August 2010
Doc ID 17863 Rev 1
1/31
www.st.com

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Summary of Contents for ST STM32F101xx series

  • Page 1 It implements a prefetch buffer that speeds up CPU code execution. It also implements the logic necessary to carry out Flash memory operations (Program/Erase). Program/Erase operations can be performed over the whole product voltage range. Read/Write protections and option bytes are also implemented. August 2010 Doc ID 17863 Rev 1 1/31 www.st.com...

  • Page 2: Table Of Contents

    Contents PM0075 Contents Overview ..........6 Features .
  • Page 3 PM0075 List of tables List of tables Table 1. Flash module organization (low-density devices) ....... . . 7 Table 2.
  • Page 4 List of figures PM0075 List of figures Figure 1. Programming procedure ........... 13 Figure 2.
  • Page 5 PM0075 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: ● Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. ● Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.

  • Page 6: Overview

    Overview PM0075 Overview Features ● up to 512 Kbytes of Flash memory ● Memory organization: – Main memory block: 4 Kbits × 64 bits for low-density devices 16 Kbits × 64 bits for medium-density devices 64 Kbits × 64 bits for high-density devices 32 Kbits ×...

  • Page 7: Table 1. Flash Module Organization (Low-Density Devices)

    PM0075 Overview Table 1. Flash module organization (low-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte Page 3 0x0800 0C00 - 0x0800 0FFF...

  • Page 8: Table 2. Flash Module Organization (Medium-Density Devices)

    Overview PM0075 Table 2. Flash module organization (medium-density devices) (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B FLASH_SR 0x4002 200C - 0x4002 200F Flash memory interface FLASH_CR...

  • Page 9: Table 4. Flash Module Organization (Connectivity Line Devices)

    STMicroelectronics and contains the boot loader which is used to reprogram the Flash memory using the USART1 serial interface. It is programmed by ST when the device is manufactured, and protected against spurious write/erase operations. For further details please refer to AN2606.
  • Page 10 Overview PM0075 The main Flash memory can be protected against different types of unwanted access (read/write/erase). There are two types of protection: ● Page Write Protection ● Read Protection Refer to Section 2.4 on page 17 for more details. During a write operation to the Flash memory, any attempt to read the Flash memory will stall the bus.

  • Page 11: Reading/Programming The Embedded Flash Memory

    PM0075 Reading/programming the embedded Flash memory Reading/programming the embedded Flash memory Introduction This section describes how to read from or program to the STM32F10xxx embedded Flash memory. Read operation The embedded Flash module can be addressed directly, as a common memory space. Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data.

  • Page 12: D-Code Interface

    Reading/programming the embedded Flash memory PM0075 In case of non-availability of a high frequency clock in the system, Flash memory accesses can be made on a half cycle of HCLK (AHB clock), the frequency of HCLK permitting (half- cycle access can only be used with a low-frequency clock of less than 8 MHz that can be obtained with the use of HSI or HSE but not of PLL).

  • Page 13: Unlocking The Flash Memory

    PM0075 Reading/programming the embedded Flash memory 2.3.2 Unlocking the Flash memory After reset, the FPEC block is protected. The FLASH_CR register is not accessible in write mode. An unlocking sequence should be written to the FLASH_KEYR register to open up the FPEC block.

  • Page 14: Flash Memory Erase

    Reading/programming the embedded Flash memory PM0075 Standard programming In this mode the CPU programs the main Flash memory by performing standard half-word write operations. The PG bit in the FLASH_CR register must be set. FPEC preliminarily reads the value at the addressed main Flash memory location and checks that it has been erased.
  • Page 15 PM0075 Reading/programming the embedded Flash memory Figure 2. Flash memory Page Erase procedure Mass Erase The Mass Erase command can be used to completely erase the user pages of the Flash memory. The information block is unaffected by this procedure. The following sequence is recommended: ●...

  • Page 16: Option Byte Programming

    Reading/programming the embedded Flash memory PM0075 Figure 3. Flash memory Mass Erase procedure 2.3.5 Option byte programming The option bytes are programmed differently from normal user addresses. The number of option bytes is limited to 8 (4 for write protection, 1 for read protection, 1 for configuration and 2 for user data storage).

  • Page 17: Protections

    PM0075 Reading/programming the embedded Flash memory The sequence is as follows: ● Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register. ● Unlock the OPTWRE bit in the FLASH_CR register. ● Set the OPTPG bit in the FLASH_CR register ●...

  • Page 18: Write Protection

    Reading/programming the embedded Flash memory PM0075 ● Pages 0-3 (for low- and medium-density devices), or pages 0-1 (for high-density and connectivity line devices) are automatically write-protected. The rest of the memory can be programmed by the code executed from the main Flash memory (for IAP, constant storage, etc.), but it is protected against write/erase (but not against mass erase) in debug mode or when booting from the embedded SRAM.

  • Page 19: Option Byte Block Write Protection

    PM0075 Reading/programming the embedded Flash memory The write protection is activated by configuring the WRP[3:0] option bytes, and then by applying a system reset to reload the new WRPx option bytes. Unprotection To disable the write protection, two application cases are provided: ●...

  • Page 20: Table 7. Option Byte Organization

    Reading/programming the embedded Flash memory PM0075 Table 7. Option byte organization Address [31:24] [23:16] [15:8] [7:0] 0x1FFF F800 nUSER USER nRDP 0x1FFF F804 nData1 Data1 nData0 Data0 0x1FFF F808 nWRP1 WRP1 nWRP0 WRP0 0x1FFF F80C nWRP3 WRP3 nWRP2 WRP2 Table 8. Description of the option bytes Flash memory Option bytes...
  • Page 21 PM0075 Reading/programming the embedded Flash memory Table 8. Description of the option bytes (continued) Flash memory Option bytes address WRPx: Flash memory write protection option bytes Bits [31:24]: nWRP3 Bits [23:16]: WRP3 (stored in FLASH_WRPR[31:24]) Bits [15:8]: nWRP2 Bits [7:0]: WRP2 (stored in FLASH_WRPR[23:16]) ●...
  • Page 22 Reading/programming the embedded Flash memory PM0075 (FLASH_WRPR). Each option byte also has its complement in the information block. During option loading, by verifying the option bit and its complement, it is possible to check that the loading has correctly taken place. If this is not the case, an option byte error (OPTERR) is generated.

  • Page 23: Register Descriptions

    PM0075 Register descriptions Register descriptions In this section, the following abbreviations are used: Table 9. Abbreviations Abbreviation Meaning read/write (rw) Software can read from and write to these bits. read-only (r) Software can only read these bits. Software can only write to this bit. Reading the bit returns the reset write-only (w) value.

  • Page 24: Fpec Key Register (Flash_Keyr)

    Register descriptions PM0075 Bit 4 PRFTBE: Prefetch buffer enable 0: Prefetch is disabled 1: Prefetch is enabled Bit 3 HLFCYA: Flash half cycle access enable 0: Half cycle is disabled 1: Half cycle is enabled Bits 2:0 LATENCY: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.

  • Page 25: Flash Status Register (Flash_Sr)

    PM0075 Register descriptions Flash status register (FLASH_SR) Address offset: 0x0C Reset value: 0x0000 0000 Reserved WRPRT Reserved Res. Res. Bits 31:6 Reserved, must be kept cleared. Bit 5 EOP: End of operation Set by hardware when a Flash operation (programming / erase) is completed. Reset by writing a 1 Note: EOP is asserted at the end of each successful program or erase operation Bit 4 WRPRTERR: Write protection error...

  • Page 26: Flash Control Register (Flash_Cr)

    Register descriptions PM0075 Flash control register (FLASH_CR) Address offset: 0x10 Reset value: 0x0000 0080 Reserved OPTWR EOPIE ERRIE LOCK STRT OPTER Reserved Res. Res. Res. Bits 31:13 Reserved, must be kept cleared. Bit 12 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1.

  • Page 27: Flash Address Register (Flash_Ar)

    PM0075 Register descriptions Flash address register (FLASH_AR) Address offset: 0x14 Reset value: 0x0000 0000 FAR[31:16] FAR[15:0] Updated by hardware with the currently/last used address. For Page Erase operations, this should be updated by software to indicate the chosen page. Bits 31:0 FAR: Flash Address Chooses the address to program when programming is selected, or a page to erase when Page Erase is selected.

  • Page 28: Write Protection Register (Flash_Wrpr)

    Register descriptions PM0075 Bit 1 RDPRT: Read protection When set, this indicates that the Flash memory is read-protected. Note: This bit is read-only. Bit 0 OPTERR: Option byte error When set, this indicates that the loaded option byte and its complement do not match. The corresponding byte and its complement are read as 0xFF in the FLASH_OBR or FLASH_WRPR register.

  • Page 29: Flash Register Map

    PM0075 Register descriptions Flash register map Table 10. Flash interface - register map and reset values Offset Register FLASH_ACR 0x000 Reserved Reset value FLASH_KEYR FKEYR[31:0] 0x004 Reset value FLASH_OPTKEYR OPTKEYR[31:0] 0x008 Reset Value FLASH_SR 0x00C Reserved Reset value FLASH_CR 0x010 Reserved Reset value FLASH_AR...

  • Page 30: Revision History

    Revision history PM0075 Revision history Table 11. Document revision history Date Revision Changes 30-Aug-2010 Initial release. Same content as PM0042 revision 8. 30/31 Doc ID 17863 Rev 1...
  • Page 31 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

This manual is also suitable for:

Stm32f103xx seriesStm32f102xx seriesStm32f105xx seriesStm32f107xx series

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