Forced Output Mode; Figure 162. Pwm Input Mode Timing - ST STM32F101 series Reference Manual

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Select the active input for TIMx_CCR1: write the CC1S bits to '01' in the TIMx_CCMR1

Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter

clear): program the CC1P and CC1NP bits to '00' (active on rising edge).

Select the active input for TIMx_CCR2: write the CC2S bits to '10' in the TIMx_CCMR1

Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the

CC2P and CC2NP bits to '11' (active on falling edge).

Select the valid trigger input: write the TS bits to '101' in the TIMx_SMCR register

(TI1FP1 selected).

Configure the slave mode controller in reset mode: write the SMS bits to '100' in the

TIMx_SMCR register.

Enable the captures: write the CC1E and CC2E bits to '1' in the TIMx_CCER register.

1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only

TI1FP1 and TI2FP2 are connected to the slave mode controller.

Forced output mode

In output mode (CCxS bits = '00' in the TIMx_CCMRx register), each output compare signal

(OCxREF and then OCx) can be forced to active or inactive level directly by software,

independently of any comparison between the output compare register and the counter.

To force an output compare signal (OCXREF/OCx) to its active level, you just need to write

'101' in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced

high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.

For example: CCxP='0' (OCx active high) => OCx is forced to high level.

The OCxREF signal can be forced low by writing the OCxM bits to '100' in the

TIMx_CCMRx register.

Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still

performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is

described in the output compare mode section below.

reset counter

DocID13902 Rev 15

General-purpose timers (TIM9 to TIM14)

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