Table 192. Error Calculation For Programmed Baud Rates - ST STM32F101 series Reference Manual

RM0008
Example 2:
To program USARTDIV = 0d25.62
This leads to:
DIV_Fraction = 16*0d0.62 = 0d9.92
The nearest real number is 0d10 = 0xA
DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19
Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625
Example 3:
To program USARTDIV = 0d50.99
This leads to:
DIV_Fraction = 16*0d0.99 = 0d15.84
The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000
Baud rate
S.No
Kbps
1. 2.4
2. 9.6
3. 19.2
4. 57.6
5. 115.2
6. 230.4 230.769
7. 460.8 461.538
8. 921.6 923.076
9. 2250
10. 4500
Note: The lower the CPU clock the lower will be the accuracy for a particular Baud rate. The upper
limit of the achievable baud rate can be fixed with this data.
Only USART1 is clocked with PCLK2 (72 MHz Max). Other USARTs are clocked with
PCLK1 (36 MHz Max).
Universal synchronous asynchronous receiver transmitter (USART)

Table 192. Error calculation for programmed baud rates

f
PCLK
Value
in programmed
Actual
in the Baud
Rate register
2.400 937.5
9.600 234.375
19.2 117.1875
57.6 39.0625
115.384 19.5
9.75
4.875
2.4375
2250 1
NA NA
DocID13902 Rev 15
= 36 MHz
% Error
=(Calculated -
Desired)B.Rate
/Desired B.Rate
0%
0%
0%
0%
0.15%
0.16%
0.16%
0.16%
0%
NA
f = 72 MHz
PCLK
Value
programmed
Actual
in the Baud
Rate register
2.4 1875
9.6 468.75
19.2 234.375
57.6 78.125
115.2 39.0625
230.769 19.5
461.538 9.75
923.076 4.875
2250 2
4500 1
% Error
0%
0%
0%
0.%
0%
0.16%
0.16%
0.16%
0%
0%
792/1128
820