Adc Regular Sequence Register 3 (Adc_Sqr3) - ST STM32F101 series Reference Manual

RM0008

11.12.11 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28
Reserved
rw rw
15 14 13 12
SQ4_0 SQ3[4:0]
rw rw rw rw
Bits 31:30
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..17) assigned as the 6th in the
sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
27 26 25
SQ6[4:0]
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11 10 9
rw rw rw
Reserved, must be kept at reset value.
DocID13902 Rev 15
Analog-to-digital converter (ADC)
24 23 22 21
SQ5[4:0]
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8 7 6 5
SQ2[4:0]
rw rw rw rw
20 19 18 17
SQ4[4:1]
rw rw rw rw
4 3 2 1
SQ1[4:0]
rw rw rw rw
16
rw
0
rw
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252