ST STM32F101 series Reference Manual page 868

Advanced arm-based 32-bit mcus

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OTG_FS Host non-periodic transmit FIFO size register

(OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0)

Address offset: 0x028

Reset value: 0x0000 0200

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

NPTXFD/TX0FD

Bits 31:16 NPTXFD: Non-periodic TxFIFO depth

Bits 15:0 NPTXFSA: Non-periodic transmit RAM start address

Bits 31:16 TX0FD: Endpoint 0 TxFIFO depth

Bits 15:0 TX0FSA: Endpoint 0 transmit RAM start address

OTG_FS non-periodic transmit FIFO/queue status register

(OTG_FS_HNPTXSTS)

Address offset: 0x02C

Reset value: 0x0008 0200

In Device mode, this register is not valid.

This read-only register contains the free space information for the non-periodic TxFIFO and

the non-periodic transmit request queue.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

This value is in terms of 32-bit words.

Minimum value is 16

Maximum value is 256

This field contains the memory start address for non-periodic transmit FIFO RAM.

This value is in terms of 32-bit words.

Minimum value is 16

Maximum value is 256

This field contains the memory start address for the endpoint 0 transmit FIFO RAM.

DocID13902 Rev 15

USB on-the-go full-speed (OTG_FS)

NPTXFSA/TX0FSA