Figure 342. Receive Bit Order - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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Ethernet (ETH): media access control (MAC) with DMA controller

Receive status word

At the end of the Ethernet frame reception, the MAC outputs the receive status to the

application (DMA). The detailed description of the receive status is the same as for

bits[31:0] in RDES0, given in

Frame length interface

In case of switch applications, data transmission and reception between the application and

MAC happen as complete frame transfers. The application layer should be aware of the

length of the frames received from the ingress port in order to transfer the frame to the

egress port. The MAC core provides the frame length of each received frame inside the

status at the end of each frame reception.

A frame length value of 0 is given for partial frames written into the Rx FIFO due to overflow.

MII/RMII receive bit order

Each nibble is transmitted to the MII from the dibit received from the RMII in the nibble

transmission order shown in

followed by the higher-order bits (D2 and D3).

RDES0: Receive descriptor Word0 on page

342. The lower-order bits (D0 and D1) are received first,

Figure 342. Receive bit order

MII_RXD[3:0]

Nibble stream

DocID13902 Rev 15

Di-bit stream