ST STM32F101 series Reference Manual page 874

Advanced arm-based 32-bit mcus

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Bits 23:16 PTXQSAV: Periodic transmit request queue space available

Bits 15:0 PTXFSAVL: Periodic transmit data FIFO space available

OTG_FS Host all channels interrupt register (OTG_FS_HAINT)

Address offset: 0x414

Reset value: 0x0000 000

When a significant event occurs on a channel, the host all channels interrupt register

interrupts the application using the host channels interrupt bit of the Core interrupt register

(HCINT bit in OTG_FS_GINTSTS). This is shown in

per channel, up to a maximum of 16 bits. Bits in this register are set and cleared when the

application sets and clears bits in the corresponding host channel-x interrupt register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 HAINT: Channel interrupts

Indicates the number of free locations available to be written in the periodic transmit request

queue. This queue holds both IN and OUT requests.

00: Periodic transmit request queue is full

01: 1 location available

10: 2 locations available

bxn: n locations available (0 ≤ n ≤ 8)

Others: Reserved

Indicates the number of free locations available to be written to in the periodic TxFIFO.

Values are in terms of 32-bit words

0000: Periodic TxFIFO is full

0001: 1 word available

0010: 2 words available

bxn: n words available (where 0 ≤ n ≤ PTXFD)

Others: Reserved

One bit per channel: Bit 0 for Channel 0, bit 15 for Channel 15

DocID13902 Rev 15

USB on-the-go full-speed (OTG_FS)

310. There is one interrupt bit