Counter Modes; Figure 148. Counter Timing Diagram With Prescaler Division Change From 1 To 2; Figure 149. Counter Timing Diagram With Prescaler Division Change From 1 To 4 - ST STM32F101 series Reference Manual

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Figure 148. Counter timing diagram with prescaler division change from 1 to 2

Figure 149. Counter timing diagram with prescaler division change from 1 to 4

16.3.2

Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller on TIM9 and TIM12) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
Prescaler control register
Write a new value in TIMx_PSC
Prescaler buffer
Prescaler counter
DocID13902 Rev 15
General-purpose timers (TIM9 to TIM14)
F7 F8 F9 FA FB FC 00
0
0
0 1
0
F7 F8 F9 FA FB FC
0
0
0 1
0
01 02 03
1
1
0 1 0 1 0 1
00 01
3
3
2 3 0 1 2 3
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