ST STM32F101 series Reference Manual page 855

Advanced arm-based 32-bit mcus

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USB on-the-go full-speed (OTG_FS)

OTG_FS USB configuration register (OTG_FS_GUSBCFG)

Address offset: 0x00C

Reset value: 0x0000 0A00

This register can be used to configure the core after power-on or a changing to host mode

or device mode. It contains USB and USB-PHY related configuration parameters. The

application must program this register before starting any transactions on either the AHB or

the USB. Do not make changes to this register after the initial programming.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Bits 31:20 Reserved, must be kept at reset value.

Bit 31 CTXPKT: Corrupt Tx packet

This bit is for debug purposes only. Never set this bit to 1.

Note: Accessible in both device and host modes.

Bit 30 FDMOD: Force device mode

Writing a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input

0: Normal mode

1: Force device mode

After setting the force bit, the application must wait at least 25 ms before the change takes

Note: Accessible in both device and host modes.

Bit 29 FHMOD: Force host mode

Writing a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin.

0: Normal mode

1: Force host mode

After setting the force bit, the application must wait at least 25 ms before the change takes

Note: Accessible in both device and host modes.

Bits 28:14 Reserved, must be kept at reset value.

Bits 13:10 TRDT: USB turnaround time

Sets the turnaround time in PHY clocks.

To calculate the value of TRDT, use the following formula:

1. if AHB clock = 72 MHz (PHY Clock is 48), the TRDT is set to 9.

2. if AHB clock = 48 MHz (PHY Clock is 48), the TRDT is set to 5.

Note: Only accessible in device mode.

TRDT = 4 × AHB clock + 1 PHY clock

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