Table 118. Fsmc_Btrx Bit Fields; Table 119. Fsmc_Bwtrx Bit Fields - ST STM32F101 series Reference Manual

RM0008
Bit No.
1
0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Table 117. FSMC_BCRx bit fields (continued)
Bit name
MUXEN 0x0
MBKEN 0x1

Table 118. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x2
DATLAT 0x0
CLKDIV 0x0
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+3 HCLK cycles) for
read accesses.
DATAST
This value cannot be 0 (minimum is 1).
ADDHLD Don't care
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET
read accesses.

Table 119. FSMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x2
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST+3 HCLK cycles for write accesses).
DATAST
This value cannot be 0 (minimum is 1).
ADDHLD Don't care
Duration of the first access phase (ADDSET+1 HCLK cycles) for
ADDSET
write accesses.
DocID13902 Rev 15
Flexible static memory controller (FSMC)
Value to set
Value to set
Value to set
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