Status Register (Usart_Sr) - ST STM32F101 series Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
27.6.1

Status register (USART_SR)

Address offset: 0x00
Reset value: 0x00C0
31 30 29
15 14 13
Reserved
Bits 31:10 Reserved, forced by hardware to 0.
Bit 9 CTS: CTS flag
Bit 8 LBD: LIN break detection flag
Note: An interrupt is generated when LBD=1 if LBDIE=1
Bit 7 TXE: Transmit data register empty
Note: This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
Bit 5 RXNE: Read data register not empty
811/1128
28 27 26 25
12 11 10 9
CTS
rc_w0
This bit is set by hardware when the
by software (by writing it to 0). An interrupt is generated if CTSIE=1 in the USART_CR3
register.
0: No change occurred on the
1: A change occurred on the
This bit is not available for UART4 & UART5.
This bit is set by hardware when the LIN break is detected. It is cleared by software (by
writing it to 0). An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
This bit is set by hardware when the content of the TDR register has been transferred into
the shift register. An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register. It
is cleared by a write to the USART_DR register.
0: Data is not transferred to the shift register
1: Data is transferred to the shift register)
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by a
software sequence (a read from the USART_SR register followed by a write to the
USART_DR register). The TC bit can also be cleared by writing a '0' to it. This clearing
sequence is recommended only for multibuffer communication.
0: Transmission is not complete
1: Transmission is complete
This bit is set by hardware when the content of the RDR shift register has been transferred to
the USART_DR register. An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
It is cleared by a read to the USART_DR register. The RXNE flag can also be cleared by
writing a zero to it. This clearing sequence is recommended only for multibuffer
communication.
0: Data is not received
1: Received data is ready to be read.
DocID13902 Rev 15
24 23 22 21
Reserved
8 7 6 5
LBD
TXE TC RXNE
rc_w0 r rc_w0 rc_w0
n
CTS input toggles, if the CTSE bit is set. It is cleared
n
CTS status line
n
CTS status line
20 19 18 17
4 3 2 1
IDLE ORE NE FE
r r r r
RM0008
16
0
PE
r