Port Configuration Register High (Gpiox_Crh) (X=A..g; Port Input Data Register (Gpiox_Idr) (X=A..g - ST STM32F101 series Reference Manual

RM0008
9.2.2

Port configuration register high (GPIOx_CRH) (x=A..G)

Address offset: 0x04
Reset value: 0x4444 4444
31 30 29 28
CNF15[1:0] MODE15[1:0]
rw rw rw rw
15 14 13 12
CNF11[1:0] MODE11[1:0]
rw rw rw rw
Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 .. 15)
23:22, 19:18, 15:14,
These bits are written by software to configure the corresponding I/O port.
11:10, 7:6, 3:2
Refer to
In input mode (MODE[1:0]=00):
00: Analog mode
01: Floating input (reset state)
10: Input with pull-up / pull-down
11: Reserved
In output mode (MODE[1:0]
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
Bits 29:28, 25:24, MODEy[1:0]: Port x mode bits (y= 8 .. 15)
21:20, 17:16, 13:12,
These bits are written by software to configure the corresponding I/O port.
9:8, 5:4, 1:0
Refer to
00: Input mode (reset state)
01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.
9.2.3

Port input data register (GPIOx_IDR) (x=A..G)

Address offset: 0x08h
Reset value: 0x0000 XXXX
31 30 29 28
15 14 13 12
IDR15 IDR14 IDR13 IDR12
r r r
Bits 31:16
Bits 15:0 IDRy: Port input data (y= 0 .. 15)
General-purpose and alternate-function I/Os (GPIOs and AFIOs)
27 26 25
CNF14[1:0] MODE14[1:0]
rw rw rw
11 10 9
CNF10[1:0] MODE10[1:0]
rw rw rw
Table 20: Port bit configuration table on page
Table 20: Port bit configuration table on page
27 26 25
11 10 9
IDR11 IDR10 IDR9
r r r r
Reserved, must be kept at reset value.
These bits are read only and can be accessed in Word mode only. They contain the input
value of the corresponding I/O port.
24 23 22
CNF13[1:0]
rw rw rw
8 7 6
CNF9[1:0]
rw rw rw
>
00):
24 23 22
Reserved
8 7 6
IDR8 IDR7 IDR6
r r r
DocID13902 Rev 15
21 20 19 18
MODE13[1:0] CNF12[1:0]
rw rw rw rw
5 4 3 2
MODE9[1:0] CNF8[1:0]
rw rw rw rw
161.
161.
21 20 19 18
5 4 3 2
IDR5 IDR4 IDR3 IDR2
r r r
17 16
MODE12[1:0]
rw rw
1 0
MODE8[1:0]
rw rw
17 16
1 0
IDR1 IDR0
r r r
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