Dual Dac 8-Bit Right Aligned Data Holding Register; (Dac_Dhr8Rd); Dac Channel1 Data Output Register (Dac_Dor1); Dac Channel2 Data Output Register (Dac_Dor2) - ST STM32F101 series Reference Manual

Digital-to-analog converter (DAC)
12.5.11

DUAL DAC 8-bit right aligned data holding register

(DAC_DHR8RD)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
DACC2DHR[7:0]
rw rw rw
Bits 31:16 Reserved.
Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specify 8-bit data for DAC channel1.
12.5.12

DAC channel1 data output register (DAC_DOR1)

Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved.
Bit 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read only, they contain data output for DAC channel1.
12.5.13

DAC channel2 data output register (DAC_DOR2)

Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved.
Bit 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read only, they contain data output for DAC channel2.
271/1128
27 26 25
11 10 9
rw rw rw rw
27 26 25
11 10 9
r r r
27 26 25
11 10 9
r r r
24 23 22
Reserved
8 7 6
rw rw rw
24 23 22
Reserved
8 7 6
DACC1DOR[11:0]
r r r
24 23 22
Reserved
8 7 6
DACC2DOR[11:0]
r r r
DocID13902 Rev 15
21 20 19 18
5 4 3 2
DACC1DHR[7:0]
rw rw rw rw
21 20 19 18
5 4 3 2
r r r r
21 20 19 18
5 4 3 2
r r r r
RM0008
17 16
1 0
rw rw
17 16
1 0
r r
17 16
1 0
r r