Dual Dac Channel Conversion; Independent Trigger Without Wave Generation; Figure 47. Dac Conversion (Sw Trigger Enabled) With Triangle Wave Generation - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR

MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be

Dual DAC channel conversion

To efficiently use the bus bandwidth in applications that require the two DAC channels at the

same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A

unique register access is then required to drive both DAC channels at the same time.

Eleven possible conversion modes are possible using the two DAC channels and these dual

registers. All the conversion modes can nevertheless be obtained using separate DHRx

registers if needed.

All modes are described in the paragraphs below.

To configure the DAC in this conversion mode, the following sequence is required:

Set the two DAC channel trigger enable bits TEN1 and TEN2

Configure different trigger sources by setting different values in the TSEL1[2:0] and

TSEL2[2:0] bits

Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,

DAC_DHR12LD or DAC_DHR8RD)

When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1

(three APB1 clock cycles later).

When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2

(three APB1 clock cycles later).

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Digital-to-analog converter (DAC)