Figure 173. Counter Timing Diagram, Internal Clock Divided By 2; Figure 174. Counter Timing Diagram, Internal Clock Divided By 4; Figure 175. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F101 series Reference Manual

Basic timers (TIM6&TIM7)
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Figure 173. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 174. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 175. Counter timing diagram, internal clock divided by N

CK_INT
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
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0035 0036 0000 0001 0002 0003
0035 0036
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RM0008
0000 0001
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