Port Output Data Register (Gpiox_Odr) (X=A; Port Bit Set/Reset Register (Gpiox_Bsrr) (X=A - ST STM32F101 series Reference Manual

General-purpose and alternate-function I/Os (GPIOs and AFIOs)
9.2.4 Port output data register (GPIOx_ODR) (x=A..G)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
15 14 13
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data (y= 0 .. 15)
These bits can be read and written by software and can be accessed in Word mode only.
Note: For atomic bit set/reset, the ODR bits can be individually set and cleared by writing to
9.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..G)
Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
BR15 BR14 BR13 BR12
w w w
15 14 13
BS15 BS14 BS13 BS12
w w w
Bits 31:16 BRy: Port x Reset bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x Set bit y (y= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit
173/1128
28 27 26 25
12 11 10 9
ODR9
rw rw rw rw
the GPIOx_BSRR register (x = A .. G).
28 27 26 25
BR11 BR10 BR9
w w w w
12 11 10 9
BS11 BS10 BS9
w w w w
DocID13902 Rev 15
24 23 22 21
Reserved
8 7 6 5
ODR8 ODR7 ODR6 ODR5
rw rw rw rw
24 23 22 21
BR8 BR7 BR6 BR5
w w w w
8 7 6 5
BS8 BS7 BS6 BS5
w w w w
20 19 18 17
4 3 2 1
ODR4 ODR3 ODR2 ODR1
rw rw rw rw
20 19 18 17
BR4 BR3 BR2 BR1
w w w w
4 3 2 1
BS4 BS3 BS2 BS1
w w w w
RM0008
16
0
ODR0
rw
16
BR0
w
0
BS0
w