ST STM32F101 series Reference Manual page 880

RM0008
Bit 2 Reserved, must be kept at reset value.
Bit 1 CHH: Channel halted
Bit 0 XFRC: Transfer completed
OTG_FS Host channel-x interrupt mask register (OTG_FS_HCINTMSKx)
(x = 0..7, where x = Channel_number)
Address offset: 0x50C + (Channel_number × 0x20)
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERRM: Data toggle error mask
Bit 9 FRMORM: Frame overrun mask
Bit 8 BBERRM: Babble error mask
Bit 7 TXERRM: Transaction error mask
Bit 6 NYET: response received interrupt mask
Bit 5 ACKM: ACK response received/transmitted interrupt mask
Bit 4 NAKM: NAK response received interrupt mask
Bit 3 STALLM: STALL response received interrupt mask
Indicates the transfer completed abnormally either because of any USB transaction error or
in response to disable request by the application.
Transfer completed normally without any errors.
Reserved
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
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USB on-the-go full-speed (OTG_FS)
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