Figure 115. Counter Timing Diagram, Internal Clock Divided By 2; Figure 116. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 117. Counter Timing Diagram, Internal Clock Divided By N - ST STM32F101 series Reference Manual

General-purpose timers (TIM2 to TIM5)

Figure 116. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
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Figure 115. Counter timing diagram, internal clock divided by 2

CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow (cnt_ovf)
Update event (UEV)
Update interrupt flag (UIF)

Figure 117. Counter timing diagram, internal clock divided by N

CK_INT
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
DocID13902 Rev 15
0003 0002 0001 0000 0001 0002 0003
0034 0035
20 1F 01
RM0008
0036 0035
00