Table 125. Fsmc_Bcrx Bit Fields; Figure 202. Synchronous Multiplexed Read Mode - Nor, Psram (Cram) - ST STM32F101 series Reference Manual

RM0008

Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)

1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access,
they are held low.
2. NWAIT polarity is set to 0.
Bit No.
31-20
19
18-16
15
14
13
12
11

Table 125. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW No effect on synchronous read
Reserved 0x0
ASCYCWAIT 0x0
EXTMOD 0x0
WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
WREN no effect on synchronous read
WAITCFG to be set according to memory
DocID13902 Rev 15
Flexible static memory controller (FSMC)
Value to set
528/1128
555