Capture/Compare Channels; Figure 124. Control Circuit In External Clock Mode 2; Figure 125. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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General-purpose timers (TIM2 to TIM5)

As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.

Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register

Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR

Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual clock of the counter is due to the

resynchronization circuit on the ETRP signal.

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a

shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and

an output stage (with comparator and output control).

The following figure gives an overview of one Capture/Compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be

used as trigger input by the slave mode controller or as the capture command. It is

prescaled before the capture register (ICxPS).

Counter clock = CK_CNT = CK_PSC

Counter register

DocID13902 Rev 15

TI1F_Falling

(from channel 2)

TI2F_falling

(from channel 2)

to the slave mode controller

/1, /2, /4, /8

(from slave mode

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