Clock Selection; Figure 118. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow); Figure 119. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32F101 series Reference Manual

RM0008

Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow)

Figure 119. Counter timing diagram, Update event with ARPE=1 (counter overflow)

15.3.3

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin (TIx)
•
External clock mode2: external trigger input (ETR).
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer1 to act as a prescaler for Timer 2. Refer to
one timer as prescaler for another on page 391
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
DocID13902 Rev 15
General-purpose timers (TIM2 to TIM5)
06 05 04 03 02 01 00 01 02 03 04 05 06 07
FD
FD
F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
FD
FD
for more details.
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36
36
36
: Using
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