Tim9/12 Capture/Compare Enable Register (Timx_Ccer) - ST STM32F101 series Reference Manual

General-purpose timers (TIM9 to TIM14)
16.4.7

TIM9/12 capture/compare enable register (TIMx_CCER)

Address offset: 0x20
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 CC2NP: Capture/Compare 2 output Polarity
Bits 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity
Bit 4 CC2E: Capture/Compare 2 output enable
Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
Note: 11: noninverted/both edges
Bit 0 CC1E: Capture/Compare 1 output enable.
447/1128
12 11 10 9
Reserved
refer to CC1NP description
refer to CC1P description
refer to CC1E description
CC1 channel configured as output: CC1NP must be kept cleared
CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define
TI1FP1/TI2FP1 polarity (refer to CC1P description).
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,
external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This
configuration must not be used for encoder mode.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
DocID13902 Rev 15
8 7 6 5
CC2NP CC2P
Res.
rw rw
4 3 2 1
CC2E CC1NP CC1P
Res.
rw rw rw
RM0008
0
CC1E
rw