I 2 C Status Register 2 (I2C_Sr2) - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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C Status register 2 (I2C_SR2)

Address offset: 0x18

Reset value: 0x0000

Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was

set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found

set in I2C_SR1 or when the STOPF bit is cleared.

Bits 15:8 PEC[7:0] Packet error checking register

Bit 7 DUALF: Dual flag (Slave mode)

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 6 SMBHOST: SMBus host header (Slave mode)

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 5 SMBDEFAULT: SMBus device default address (Slave mode)

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 4 GENCALL: General call address (Slave mode)

– Cleared by hardware after a Stop condition or repeated Start condition, or when PE=0.

Bit 3 Reserved, must be kept at reset value

This register contains the internal PEC when ENPEC=1.

0: Received address matched with OAR1

1: Received address matched with OAR2

0: No SMBus Host address

1: SMBus Host address received when SMBTYPE=1 and ENARP=1.

0: No SMBus Device Default address

1: SMBus Device Default address received when ENARP=1

0: No General Call

1: General Call Address received when ENGC=1

DocID13902 Rev 15

Inter-integrated circuit (I

C) interface