Boot Configuration; Table 9. Boot Modes - ST STM32F101 series Reference Manual

Memory and bus architecture
Flash access control register (FLASH_ACR)
Address offset: 0x00
Reset value: 0x0000 0030
31 30 29 28
15 14 13 12
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 PRFTBS: Prefetch buffer status
Bit 4 PRFTBE: Prefetch buffer enable
Bit 3 HLFCYA: Flash half cycle access enable
Bits 2:0 LATENCY: Latency
3.4

Boot configuration

In the STM32F10xxx, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in
Boot mode selection pins
BOOT1 BOOT0
x
0
1
61/1128
27 26 25
11 10 9
Reserved
This bit provides the status of the prefetch buffer.
0: Prefetch buffer is disabled
1: Prefetch buffer is enabled
0: Prefetch is disabled
1: Prefetch is enabled
0: Half cycle is disabled
1: Half cycle is enabled
These bits represent the ratio of the SYSCLK (system clock) period to the Flash access
time.
000 Zero wait state, if 0 < SYSCLK≤ 24 MHz
001 One wait state, if 24 MHz < SYSCLK ≤ 48 MHz
010 Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz
Table 9.

Table 9. Boot modes

Boot mode
0 Main Flash memory
1 System memory
1 Embedded SRAM
24 23 22
Reserved
8 7 6
Main Flash memory is selected as boot space
System memory is selected as boot space
Embedded SRAM is selected as boot space
DocID13902 Rev 15
21 20 19
5 4 3
PRFTBS PRFTBE HLFCYA
r rw rw
Aliasing
RM0008
18 17 16
2 1 0
LATENCY
rw rw rw