Adc Sample Time Register 2 (Adc_Smpr2); Adc Injected Channel Data Offset Register X (Adc_Jofrx)(X=1 - ST STM32F101 series Reference Manual

RM0008
11.12.5

ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28
Reserved SMP9[2:0]
Res. rw rw
15 14 13 12
SMP
SMP4[2:0]
5_0
rw rw rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for each channel.
During sample cycles channel selection bits must remain unchanged.
000: 1.5 cycles
001: 7.5 cycles
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles
Note: ADC3 analog input Channel9 is connected to V
11.12.6

ADC injected channel data offset register x (ADC_JOFRx)(x=1..4)

Address offset: 0x14-0x20
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
27 26 25
SMP8[2:0]
rw rw rw
11 10 9
SMP3[2:0]
rw rw rw
27 26 25
11 10 9
rw rw rw
Reserved, must be kept at reset value.
DocID13902 Rev 15
Analog-to-digital converter (ADC)
24 23 22 21
SMP7[2:0]
rw rw rw rw
8 7 6 5
SMP2[2:0]
rw rw rw rw
SS
24 23 22 21
Reserved
8 7 6 5
JOFFSETx[11:0]
rw rw rw rw
20 19 18
SMP6[2:0]
rw rw rw
4 3 2
SMP1[2:0] SMP0[2:0]
rw rw rw
.
20 19 18
4 3 2
rw rw rw
17 16
SMP5[2:1]
rw rw
1 0
rw rw
17 16
1 0
rw rw
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