Tim1&Tim8 Registers; Tim1&Tim8 Control Register 1 (Timx_Cr1) - ST STM32F101 series Reference Manual

Advanced-control timers (TIM1&TIM8)
14.4 TIM1&TIM8 registers
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
15 14 13
Reserved
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:8 CKD[1:0]: Clock division
Bit 7 ARPE: Auto-reload preload enable
Bits 6:5 CMS[1:0]: Center-aligned mode selection
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
Bit 4 DIR: Direction
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
Bit 3 OPM: One pulse mode
333/1128
Section 2.1 on page 47
12 11 10 9
CKD[1:0]
rw
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and the
dead-time and sampling clock (t
(ETR, TIx),
00: t =t
DTS CK_INT
01: t =2*t
DTS CK_INT
10: t =4*t
DTS CK_INT
11: Reserved, do not program this value
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
the counter is enabled (CEN=1)
0: Counter used as upcounter
1: Counter used as downcounter
mode.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)
for a list of abbreviations used in register descriptions.
8 7 6
ARPE CMS[1:0]
rw rw rw
)used by the dead-time generators and the digital filters
DTS
DocID13902 Rev 15
5 4 3 2
DIR OPM URS
rw rw rw rw
RM0008
1 0
UDIS CEN
rw rw