Analog Watchdog; Scan Mode; Table 66. Analog Watchdog Channel Selection; Figure 24. Analog Watchdog Guarded Area - ST STM32F101 series Reference Manual

RM0008
11.3.7

Analog watchdog

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in the
12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be
enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The comparison is done before the alignment (see
The analog watchdog can be enabled on one or more channels by configuring the
ADC_CR1 register as shown in
Channels to be guarded by analog
None
All injected channels
All regular channels
All regular and injected channels
(1)
Single
(1)
Single
(1)
Single
1. Selected by AWDCH[4:0] bits
11.3.8

Scan mode

This mode is used to scan a group of analog channels.
Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular
channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for
each channel of the group. After each end of conversion the next channel of the group is
converted automatically. If the CONT bit is set, conversion does not stop at the last selected
group channel but continues again from the first selected group channel.
When using scan mode, DMA bit must be set and the direct memory access controller is
used to transfer the converted data of regular group channels to SRAM after each update of
the ADC_DR register.
The injected channel converted data is always stored in the ADC_JDRx registers.

Figure 24. Analog watchdog guarded area

Analog voltage
High threshold
Low threshold

Table 66. Analog watchdog channel selection

watchdog
injected channel
regular channel
regular or injected channel
DocID13902 Rev 15
Table 66.
Guarded area
ADC_CR1 register control bits (x = don't care)
AWDSGL bit
x
0
0
0
1
1
1
Analog-to-digital converter (ADC)
Section
HTR
LTR
AWDEN bit JAWDEN bit
0
0
1
1
0
1
1
11.5).
0
1
0
1
1
0
1
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