ST STM32F101 series Reference Manual page 676

Advanced arm-based 32-bit mcus
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RM0008
CAN TX mailbox identifier register (CAN_TIxR) (x=0..2)
Address offsets: 0x180, 0x190, 0x1A0
Reset value: 0xXXXX XXXX (except bit 0, TXRQ = 0)
All TX registers are write protected when the mailbox is pending transmission (TMEx reset).
This register also implements the TX request control (bit 0) - reset value 0.
31
30
29
rw
rw
rw
15
14
13
rw
rw
rw
Bits 31:21 STID[10:0]/EXID[28:18]
Bits 20:3 EXID[17:0]: Extended identifier
Bit 2 IDE
Bit 1 RTR
Bit 0 TXRQ
28
27
26
25
STID[10:0]/EXID[28:18]
rw
rw
rw
rw
12
11
10
9
EXID[12:0]
rw
rw
rw
rw
:
Standard identifier or extended identifier
The standard identifier or the MSBs of the extended identifier (depending on the IDE bit
value).
The LSBs of the extended identifier.
:
Identifier extension
This bit defines the identifier type of message in the mailbox.
0: Standard identifier.
1: Extended identifier.
:
Remote transmission request
0: Data frame
1: Remote frame
:
Transmit mailbox request
Set by software to request the transmission for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.
DocID13902 Rev 15
Controller area network (bxCAN)
24
23
22
21
rw
rw
rw
rw
8
7
6
5
rw
rw
rw
rw
20
19
18
17
EXID[17:13]
rw
rw
rw
rw
4
3
2
1
IDE
RTR
rw
rw
rw
rw
16
rw
0
TXRQ
rw
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