Otg_Fs Power And Clock Gating Control Register; (Otg_Fs_Pcgcctl) - ST STM32F101 series Reference Manual

RM0008
STUPCNT: SETUP packet count
Bit 28:19 PKTCNT: Packet count
Bits 18:0 XFRSIZ: Transfer size
28.16.5

OTG_FS power and clock gating control register

(OTG_FS_PCGCCTL)

Address offset: 0xE00
Reset value: 0x0000 0000
This register is available in host and device modes.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit 31:5 Reserved, must be kept at reset value.
Bit 4 PHYSUSP: PHY Suspended
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 GATEHCLK: Gate HCLK
Bit 0 STPPCLK: Stop PHY clock
Applies to control OUT Endpoints only.
This field specifies the number of back-to-back SETUP data packets the endpoint can
receive.
01: 1 packet
10: 2 packets
11: 3 packets
Indicates the total number of USB packets that constitute the Transfer Size amount of data
for this endpoint.
This field is decremented every time a packet (maximum size or short packet) is written to
the RxFIFO.
This field contains the transfer size in bytes for the current endpoint. The core only interrupts
the application after it has exhausted the transfer size amount of data. The transfer size can
be set to the maximum packet size of the endpoint, to be interrupted at the end of each
packet.
The core decrements this field every time a packet is read from the RxFIFO and written to
the external memory.
Reserved
Indicates that the PHY has been suspended. This bit is updated once the PHY is suspended
after the application has set the STPPCLK bit (bit 0).
The application sets this bit to gate HCLK to modules other than the AHB Slave and Master
and wakeup logic when the USB is suspended or the session is not valid. The application
clears this bit when the USB is resumed or a new session starts.
The application sets this bit to stop the PHY clock when the USB is suspended, the session
is not valid, or the device is disconnected. The application clears this bit when the USB is
resumed or a new session starts.
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