Dac Register Map; Table 75. Dac Register Map - ST STM32F101 series Reference Manual
Advanced arm-based 32-bit mcus
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- Reference manual (501 pages) ,
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RM0008
12.5.14
DAC register map
The following table summarizes the DAC registers.
Offset
Register
DAC_CR
0x00
Reset value
DAC_SWTRIGR
0x04
Reset value
DAC_DHR12R1
0x08
Reset value
DAC_DHR12L1
0x0C
Reset value
DAC_DHR8R1
0x10
Reset value
DAC_DHR12R2
0x14
Reset value
DAC_DHR12L2
0x18
Reset value
DAC_DHR8R2
0x1C
DAC_DHR12RD
0x20
Reset value
DAC_DHR12LD
0x24
Reset value
0
DAC_DHR8RD
0x28
Reset value
DAC_DOR1
0x2C
Reset value
DAC_DOR2
0x30
Reset value
Note:
Refer to
Table 75. DAC register map
WAV
MAMP2[3:0]
E2[2:
Res.
0
0
0
0
0
0
Reserved
Reserved
DACC2DHR[11:0]
Reserved
0
0
0
0
0
DACC2DHR[11:0]
0
0
0
0
0
0
0
0
Reserved
Table 3 on page 51
for the register boundary addresses.
TSEL2[2:
0]
0]
0
0
0
0
0
0
0
Reserved
Reserved
0
Reserved
Reserved
0
Reserved
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
Reserved
Reserved
DocID13902 Rev 15
Digital-to-analog converter (DAC)
WAV
MAMP1[3:0]
E1[2:
Res.
0
0
0
0
0
0
DACC1DHR[11:0]
0
0
0
0
0
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
0
DACC2DHR[11:0]
0
0
0
0
0
DACC2DHR[11:0]
0
0
0
0
0
0
0
0
0
DACC1DHR[11:0]
Reserved
0
0
0
0
0
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
DACC2DHR[7:0]
0
0
0
0
0
0
0
0
DACC1DOR[11:0]
0
0
0
0
0
DACC2DOR[11:0]
0
0
0
0
0
TSEL1
[2:0]
0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
DACC1DHR[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
DACC2DHR[7:0]
0 0
0
0 0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
DACC1DHR[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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