ST STM32F101 series Reference Manual page 552

RM0008
Bits 31:24 IOHIZx: I/O x databus HiZ time
Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
start of a PC Card write access to I/O space on socket x. Only valid for write transaction:
0000 0000: 0 HCLK cycle
1111 1111: 255 HCLK cycles (default value after reset)
Bits 23:16 IOHOLDx: I/O x hold time
Defines the number of HCLK clock cycles to hold address (and data for write access) after
the command deassertion (NWE, NOE), for PC Card read or write access to I/O space on
socket x:
0000 0000: reserved
0000 0001: 1 HCLK cycle
1111 1111: 255 HCLK cycles (default value after reset)
Bits 15:8 IOWAITx: I/O x wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE,
SMNOE), for PC Card read or write access to I/O space on socket x. The duration for
command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the
programmed value of HCLK:
0000 0000: reserved, do not use this value
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT)
(default value after reset)
Bits 7:0 IOSETx: I/O x setup time
Defines the number of HCLK (+1) clock cycles to set up the address before the command
assertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:
0000 0000: 1 HCLK cycle
1111 1111: 256 HCLK cycles (default value after reset)
ECC result registers 2/3 (FSMC_ECCR2/3)
Address offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3
Reset value: 0x0000 0000
These registers contain the current error correction code value computed by the ECC
computation modules of the FSMC controller (one module per NAND Flash memory bank).
When the CPU reads the data from a NAND Flash memory page at the correct address
(refer to
memory), the data read from or written to the NAND Flash are processed automatically by
ECC computation module. At the end of X bytes read (according to the ECCPS field in the
FSMC_PCRx registers), the CPU must read the computed ECC value from the
FSMC_ECCx registers, and then verify whether these computed parity data are the same
as the parity value recorded in the spare area, to determine whether a page is valid, and, to
correct it if applicable. The FSMC_ECCRx registers should be cleared after being read by
setting the ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set
to one.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Section 21.6.6: Computation of the error correction code (ECC) in NAND Flash
Flexible static memory controller (FSMC)
ECCx
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