ST STM32F101 series Reference Manual page 105

Low-, medium-, high- and XL-density reset and clock control (RCC)
Bit 11 HSERDYIE: HSE ready interrupt enable
Bit 10 HSIRDYIE: HSI ready interrupt enable
Bit 9 LSERDYIE: LSE ready interrupt enable
Bit 8 LSIRDYIE: LSI ready interrupt enable
Bit 7 CSSF: Clock security system interrupt flag
Bits 6:5
Bit 4 PLLRDYF: PLL ready interrupt flag
Bit3 HSERDYF: HSE ready interrupt flag
105/1128
Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the external 32 kHz
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by internal RC 40 kHz
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Set by hardware when a failure is detected in the external 4-16 MHz oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Reserved, must be kept at reset value.
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the external 4-16 MHz oscillator
1: Clock ready interrupt caused by the external 4-16 MHz oscillator
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