Connectivity Line Devices: Reset And Clock Control (Rcc); Reset; System Reset - ST STM32F101 series Reference Manual

Connectivity line devices: reset and clock control (RCC)

8 Connectivity line devices: reset and clock control
(RCC)
Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
High-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 256 and 512 Kbytes.
XL-density devices are STM32F101xx and STM32F103xx microcontrollers where the
Flash memory density ranges between 768 Kbytes and 1 Mbyte.
Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
This Section applies to all connectivity line devices, unless otherwise specified.
8.1

Reset

There are three types of reset, defined as system reset, power reset and backup domain
reset.
8.1.1

System reset

A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see
A system reset is generated when one of the following events occurs:
1. A low level on the NRST pin (external reset)
2. Window watchdog end of count condition (WWDG reset)
3. Independent watchdog end of count condition (IWDG reset)
4. A software reset (SW reset) (see
5. Low-power management reset (see
The reset source can be identified by checking the reset flags in the Control/Status register,
RCC_CSR (see
Software reset
The SYSRESETREQ bit in Cortex
must be set to force a software reset on the device. Refer to the STM32F10xxx Cortex
programming manual (see
123/1128
Section 8.3.10: Control/status register
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Related documents on page
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Software reset)
Low-power management
(RCC_CSR)).
1) for more details.
RM0008
Figure 4).
reset)
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