Error Management - ST STM32F101 series Reference Manual

Direct memory access controller (DMA)
Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1) (continued)
Number
Desti-
Source of data
nation
port items to
port
width transfer
width
(NDT)
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
32 16 4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC
Addressing an AHB peripheral that does not support byte or halfword write
operations
When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on
the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does
not support byte or halfword write operations (when HSIZE is not used by the peripheral)
and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two
examples below:
•
To write the halfword "0xABCD", the DMA sets the HWDATA bus to "0xABCDABCD"
with HSIZE = HalfWord
•
To write the byte "0xAB", the DMA sets the HWDATA bus to "0xABABABAB" with
HSIZE = Byte
Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the
HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit
APB operation in the following manner:
•
an AHB byte write operation of the data "0xB0" to 0x0 (or to 0x1, 0x2 or 0x3) will be
converted to an APB word write operation of the data "0xB0B0B0B0" to 0x0
•
an AHB halfword write operation of the data "0xB1B0" to 0x0 (or to 0x2) will be
converted to an APB word write operation of the data "0xB1B0B1B0" to 0x0
For instance, if you want to write the APB backup registers (16-bit registers aligned to a 32-
bit address boundary), you must configure the memory source size (MSIZE) to "16-bit" and
the peripheral destination size (PSIZE) to "32-bit".
13.3.5

Error management

A DMA transfer error can be generated by reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or a write access, the faulty
channel is automatically disabled through a hardware clear of its EN bit in the corresponding
Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag
(TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error
interrupt enable bit (TEIE) in the DMA_CCRx register is set.
279/1128
Source content:
address / data
1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[7:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[7:0] @0x1
3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[7:0] @0x2
4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[7:0] @0x3
1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0
2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4
3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8
4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC
DocID13902 Rev 15
Transfer operations
RM0008
Destination content:
address / data
@0x0 / B1B0
@0x2 / B5B4
@0x4 / B9B8
@0x6 / BDBC
@0x0 / B3B2B1B0
@0x4 / B7B6B5B4
@0x8 / BBBAB9B8
@0xC / BFBEBDBC