Apb1 Peripheral Reset Register (Rcc_Apb1Rstr) - ST STM32F101 series Reference Manual

Low-, medium-, high- and XL-density reset and clock control (RCC)
7.3.5

APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
DAC PWR
RST RST
Reserved
rw
15 14 13
SPI3 SPI2
RST RST
Reserved
rw rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DACRST: DAC interface reset
Bit 28 PWRRST: Power interface reset
Bit 27 BKPRST: Backup interface reset
Bit 26 Reserved, must be kept at reset value.
Bit 25 CANRST: CAN reset
Bit 24 Reserved, always read as 0.
Bit 23 USBRST: USB reset
Bit 22 I2C2RST: I2C2 reset
Bit 21 I2C1RST: I2C1 reset
109/1128
28 27 26 25
BKP CAN
RST RST
Res.
rw rw rw
12 11 10 9
WWDG
RST
Reserved
rw
Set and cleared by software.
0: No effect
1: Reset DAC interface
Set and cleared by software.
0: No effect
1: Reset power interface
Set and cleared by software.
0: No effect
1: Reset backup interface
Set and cleared by software.
0: No effect
1: Reset CAN
Set and cleared by software.
0: No effect
1: Reset USB
Set and cleared by software.
0: No effect
1: Reset I2C2
Set and cleared by software.
0: No effect
1: Reset I2C1
24 23 22
USB I2C2
RST RST
Res.
rw rw
8 7 6
TIM14 TIM13 TIM12
RST RST RST
rw rw rw
DocID13902 Rev 15
21 20 19 18
USART
I2C1 UART5 UART4
3
RST RST RST
RST
rw rw rw rw
5 4 3 2
TIM7 TIM6 TIM5 TIM4
RST RST RST RST
rw rw rw rw
RM0008
17 16
USART
2
Res.
RST
rw
1 0
TIM3 TIM2
RST RST
rw rw