Figure 29. Dual Adc Block Diagram - ST STM32F101 series Reference Manual

RM0008
ADCx_IN0
ADCx_IN1
ADCx_IN15
EXTI_11
EXTI_15
1.
External triggers are present on ADC2 but are not shown for the purposes of this diagram.
2.
In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted data over
the entire 32 bits.

Figure 29. Dual ADC block diagram

GPIO
Ports
Temp. sensor
V
REFINT
Start trigger mux
(regular group)
Start trigger mux
(injected group)
DocID13902 Rev 15
Analog-to-digital converter (ADC)
Regular data register
Regular
channels
injected
channels
internal triggers
Regular data register
Regular
channels
Injected
channels
Dual mode
control
ADC1 (Master)
(1)
(12 bits)
(16 bits)
Injected data registers
(4 x 16 bits)
ADC2 (Slave)
(2)
(16 bits)
Injected data registers
(4 x 16 bits)
228/1128
252