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ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and

Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32F101xx, STM32F102xx, STM32F103xx and

STM32F105xx/STM32F107xx microcontroller memory and peripherals. The STM32F101xx,

STM32F102xx, STM32F103xx and STM32F105xx/STM32F107xx will be referred to as

STM32F10xxx throughout the document, unless otherwise specified.

The STM32F10xxx is a family of microcontrollers with different memory sizes, packages

and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

low-, medium-, high- and XL-density STM32F101xx and STM32F103xx datasheets, to the

low- and medium-density STM32F102xx datasheets and to the

STM32F105xx/STM32F107xx connectivity line datasheet.

For information on programming, erasing and protection of the internal Flash memory

please refer to:

•

PM0075, the Flash programming manual for low-, medium- high-density and

connectivity line STM32F10xxx devices

•

PM0068, the Flash programming manual for XL-density STM32F10xxx devices.

For information on the ARM

M3 programming manual (PM0056).

Related documents

Available from www.st.com:

• STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and

datasheets

• STM32F10xxx Cortex

• STM32F10xxx Flash programming manual (PM0075)

• STM32F10xxx XL-density Flash programming manual (PM0068)

June 2014

STM32F107xx advanced ARM

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Cortex

®

-M3 programming manual (PM0056)

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Reference manual

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-M3 core, please refer to the STM32F10xxx Cortex

RM0008

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Summary of Contents for ST STM32F101 series

Page 1 ® For information on the ARM Cortex -M3 core, please refer to the STM32F10xxx Cortex M3 programming manual (PM0056). Related documents Available from www.st.com: • STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx/STM32F107xx and datasheets ® • STM32F10xxx Cortex -M3 programming manual (PM0056) • STM32F10xxx Flash programming manual (PM0075) •...
Page 2: Table Of Contents
RM0008 Contents Contents Overview of the manual ........40 Documentation conventions .
Page 3 Contents RM0008 5.2.2 Programmable voltage detector (PVD) ......70 Low-power modes ......... . 72 5.3.1 Slowing down system clocks .
Page 4 RM0008 Contents 7.2.4 LSE clock ..........96 7.2.5 LSI clock .
Page 5 Contents RM0008 8.3.1 Clock control register (RCC_CR) ......132 8.3.2 Clock configuration register (RCC_CFGR) ..... 134 8.3.3 Clock interrupt register (RCC_CIR) .
Page 6 RM0008 Contents 9.3.2 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 ..175 9.3.3 CAN1 alternate function remapping ......176 9.3.4 CAN2 alternate function remapping .
Page 7 Contents RM0008 10.3.6 Pending register (EXTI_PR) ....... . 212 10.3.7 EXTI register map .
Page 8 RM0008 Contents 11.12.2 ADC control register 1 (ADC_CR1) ......237 11.12.3 ADC control register 2 (ADC_CR2) ......239 11.12.4 ADC sample time register 1 (ADC_SMPR1) .
Page 9 Contents RM0008 12.4.9 Simultaneous trigger with different LFSR generation ... . . 263 12.4.10 Simultaneous trigger with same triangle generation ....263 12.4.11 Simultaneous trigger with different triangle generation .
Page 10 RM0008 Contents 13.4 DMA registers ..........284 13.4.1 DMA interrupt status register (DMA_ISR) .
Page 11 Contents RM0008 14.4 TIM1&TIM8 registers ........333 14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) .
Page 12 RM0008 Contents 15.3.11 Clearing the OCxREF signal on an external event ....384 15.3.12 Encoder interface mode ........385 15.3.13 Timer input XOR function .
Page 13 Contents RM0008 16.3.5 Input capture mode ........428 16.3.6 PWM input mode (only for TIM9/12) .
Page 14 RM0008 Contents Basic timers (TIM6&TIM7) ........461 17.1 TIM6&TIM7 introduction .
Page 15 Contents RM0008 Independent watchdog (IWDG) ......485 19.1 IWDG introduction ......... 485 19.2 IWDG main features .
Page 16 RM0008 Contents 21.5.1 External memory interface signals ......505 21.5.2 Supported memories and transactions ......506 21.5.3 General timing rules .
Page 17 Contents RM0008 22.4.13 SD I/O mode ..........587 22.4.14 Commands and responses .
Page 18 RM0008 Contents 22.9.14 SDIO FIFO counter register (SDIO_FIFOCNT) ....610 22.9.15 SDIO data FIFO register (SDIO_FIFO) ......611 22.9.16 SDIO register map .
Page 19 Contents RM0008 24.5.3 Loop back combined with silent mode ......651 24.6 Debug mode ..........652 24.7 bxCAN functional description .
Page 20 RM0008 Contents 25.4.1 S general description ........714 25.4.2 Supported audio protocols .
Page 21 Contents RM0008 26.6.1 C Control register 1 (I2C_CR1) ......765 26.6.2 C Control register 2 (I2C_CR2) ......767 26.6.3 C Own address register 1 (I2C_OAR1) .
Page 22 RM0008 Contents 27.6.5 Control register 2 (USART_CR2) ......816 27.6.6 Control register 3 (USART_CR3) ......817 27.6.7 Guard time and prescaler register (USART_GTPR) .
Page 23 Contents RM0008 28.12 Host FIFO architecture ........840 28.12.1 Host Rx FIFO .
Page 24 RM0008 Contents 29.4.2 Media-independent interface: MII ......966 29.4.3 Reduced media-independent interface: RMII ....968 29.4.4 MII/RMII selection .
Page 25 Contents RM0008 31.1 Overview ..........1068 31.2 Reference ARM®...
Page 26 RM0008 Contents 31.15.4 Configuration example ........1090 31.16 MCU debug component (DBGMCU) .
Page 27 List of tables RM0008 List of tables Table 1. Sections related to each STM32F10xxx product ....... . 40 Table 2.
Page 28 RM0008 List of tables Table 49. TIM11 remapping ............180 Table 50.
Page 29 List of tables RM0008 Table 100. NOR/PSRAM bank selection ..........502 Table 101.
Page 30 RM0008 List of tables Table 151. Erase size field ............586 Table 152.
Page 31 List of tables RM0008 Table 202. Host-mode control and status registers (CSRs) ....... . 847 Table 203.
Page 32 RM0008 List of figures List of figures Figure 1. System architecture (low-, medium-, XL-density devices) ......48 Figure 2.
Page 33 List of figures RM0008 Figure 49. DMA block diagram in low-, medium- high- and XL-density devices ....275 Figure 50. DMA1 request mapping ..........281 Figure 51.
Page 34 RM0008 List of figures Figure 99. Control circuit in external clock mode 2 + trigger mode ......332 Figure 100.
Page 35 List of figures RM0008 Figure 151. Counter timing diagram, internal clock divided by 2 ......423 Figure 152.
Page 36 RM0008 List of figures Figure 199. Asynchronous wait during a read access ........524 Figure 200.
Page 37 List of figures RM0008 discontinuous transfers ........... 706 Figure 246.
Page 38 RM0008 List of figures Figure 297. Reception using DMA ........... . 807 Figure 298.
Page 39 List of figures RM0008 Figure 349. System time update using the Fine correction method......997 Figure 350.
Page 40: Overview Of The Manual
RM0008 Overview of the manual Overview of the manual Legend for Table • The section in each row applies to products in columns marked with “ " Table 1. Sections related to each STM32F10xxx product Section 2: Documentation • • •...
Page 41 Overview of the manual RM0008 Table 1. Sections related to each STM32F10xxx product (continued) Section 11: Analog-to- • • • • • • • • • • digital converter (ADC) Section 12: Digital-to- • • • • analog converter (DAC) Section 14: Advanced- •...
Page 42 RM0008 Overview of the manual Table 1. Sections related to each STM32F10xxx product (continued) Section 24: Controller · · · · · area network (bxCAN) Section 25: Serial • • • • • • • • • • peripheral interface (SPI) Section 26: Inter- •...
Page 43: Table 2. Sections Related To Each Peripheral
Overview of the manual RM0008 Legend for Table The section in this row must be read when using the peripherals in columns • • marked with “ " The section in this row can optionally be read when using the peripherals in ...
Page 44 RM0008 Overview of the manual Table 2. Sections related to each peripheral (continued) Section 9: General- purpose and alternate-  • • • • • • • • • • • • • • • • • à function I/Os (GPIOs and AFIOs) Section 10: Interrupts ...
Page 45 Overview of the manual RM0008 Table 2. Sections related to each peripheral (continued) Section 19: Independent watchdog · (IWDG) Section 20: Window · watchdog (WWDG) Section 21: Flexible static memory controller · (FSMC) Section 1: Secure digital input/output · interface (SDIO) Section 23: Universal serial bus full-speed ·...
Page 46 RM0008 Overview of the manual Table 2. Sections related to each peripheral (continued) Section 28: USB on- the-go full-speed · (OTG_FS) Section 29: Ethernet (ETH): media access · control (MAC) with DMA controller Section 30: Device electronic signature Section 31: Debug ...
Page 47: Documentation Conventions
Documentation conventions RM0008 Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1.
Page 48: Memory And Bus Architecture
RM0008 Memory and bus architecture Memory and bus architecture System architecture In low-, medium-, high- and XL-density devices, the main system consists of: • Four masters: ® – Cortex -M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) •...
Page 49: Figure 2. System Architecture In Connectivity Line Devices
Memory and bus architecture RM0008 In connectivity line devices the main system consists of: • Five masters: ® – Cortex -M3 core DCode bus (D-bus) and System bus (S-bus) – GP-DMA1 & 2 (general-purpose DMA) – Ethernet DMA • Three slaves: –...
Page 50: Memory Organization
RM0008 Memory and bus architecture DCode bus ® This bus connects the DCode bus (literal load and debug access) of the Cortex -M3 core to the Flash memory Data interface. System bus ® This bus connects the system bus of the Cortex -M3 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.
Page 51: Memory Map
Memory and bus architecture RM0008 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 3 gives the boundary addresses of the peripherals available in all STM32F10xxx devices. Table 3. Register boundary addresses Boundary address Peripheral Register map...
Page 52 RM0008 Memory and bus architecture Table 3. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4001 5800 - 0x4001 7FFF Reserved 0x4001 5400 - 0x4001 57FF TIM11 timer Section 16.5.10 on page 459 0x4001 5000 - 0x4001 53FF TIM10 timer Section 16.5.10 on page 459 0x4001 4C00 - 0x4001 4FFF TIM9 timer...
Page 53 Memory and bus architecture RM0008 Table 3. Register boundary addresses (continued) Boundary address Peripheral Register map 0x4000 7800 - 0x4000 FFFF Reserved 0x4000 7400 - 0x4000 77FF Section 12.5.14 on page 272 0x4000 7000 - 0x4000 73FF Power control PWR Section 5.4.3 on page 80 0x4000 6C00 - 0x4000 6FFF Backup registers (BKP)
Page 54: Embedded Sram
RM0008 Memory and bus architecture 3.3.1 Embedded SRAM The STM32F10xxx features up to 96 Kbytes of static SRAM. It can be accessed as bytes, half-words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000. 3.3.2 Bit banding ®...
Page 55: Embedded Flash Memory
Memory and bus architecture RM0008 3.3.3 Embedded Flash memory The high-performance Flash memory module has the following key features: • For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read- while-write (RWW) capability: – bank 1: fixed size of 512 Kbytes –...
Page 56: Table 5. Flash Module Organization (Medium-Density Devices)
RM0008 Memory and bus architecture Table 4. Flash module organization (low-density devices) (continued) Block Name Base addresses Size (bytes) System memory 0x1FFF F000 - 0x1FFF F7FF 2 Kbytes Information block Option Bytes 0x1FFF F800 - 0x1FFF F80F FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR...
Page 57: Table 6. Flash Module Organization (High-Density Devices)
Memory and bus architecture RM0008 Table 6. Flash module organization (high-density devices) Block Name Base addresses Size (bytes) Page 0 0x0800 0000 - 0x0800 07FF 2 Kbytes Page 1 0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 2 0x0800 1000 - 0x0800 17FF 2 Kbytes Page 3 0x0800 1800 - 0x0800 1FFF...
Page 58: Table 8. Xl-Density Flash Module Organization
RM0008 Memory and bus architecture Table 7. Flash module organization (connectivity line devices) (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B FLASH_SR 0x4002 200C - 0x4002 200F Flash memory interface FLASH_CR...
Page 59 Memory and bus architecture RM0008 Table 8. XL-density Flash module organization (continued) Block Name Base addresses Size (bytes) FLASH_ACR 0x4002 2000 - 0x4002 2003 FLASH_KEYR 0x4002 2004 - 0x4002 2007 FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B FLASH_SR 0x4002 200C - 0x4002 200F FLASH_CR 0x4002 2010 - 0x4002 2013 FLASH_AR...
Page 60 RM0008 Memory and bus architecture used only with a low-frequency clock of 8 MHz or less. It can be generated from the HSI or the HSE but not from the PLL. The prefetch buffer must be kept on when using a prescaler different from 1 on the AHB clock.
Page 61: Boot Configuration
Memory and bus architecture RM0008 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0030 Reserved PRFTBS PRFTBE HLFCYA LATENCY Reserved Bits 31:6 Reserved, must be kept at reset value. Bit 5 PRFTBS: Prefetch buffer status This bit provides the status of the prefetch buffer. 0: Prefetch buffer is disabled 1: Prefetch buffer is enabled Bit 4 PRFTBE: Prefetch buffer enable...
Page 62 Bank2 base address. (0x0808 0000) using the NVIC exception table and offset register. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory with one of the available serial interfaces: •...
Page 63 Memory and bus architecture RM0008 The USART peripheral operates with the internal 8 MHz oscillator (HSI). The CAN and USB OTG FS, however, can only function if an external 8 MHz, 14.7456 MHz or 25 MHz clock (HSE) is present. Note: For further details, please refer to AN2606.
Page 64: Crc Calculation Unit
RM0008 CRC calculation unit CRC calculation unit Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 65: Crc Functional Description
CRC calculation unit RM0008 CRC functional description The CRC calculation unit mainly consists of a single 32-bit data register, which: • is used as an input register to enter new data in the CRC calculator (when writing into the register) •...
Page 66: Control Register (Crc_Cr)
RM0008 CRC calculation unit Bits 31:8 Reserved, must be kept at reset value. Bits 7:0 General-purpose 8-bit data register bits Can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register.
Page 67: Power Control (Pwr)
Power control (PWR) RM0008 Power control (PWR) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 68: Independent A/D And D/A Converter Supply And Reference Voltage
RM0008 Power control (PWR) Figure 4. Power supply overview domain REF- A/D converter (from 2.4 V up to V D/A converter REF+ Temp. sensor Reset block domain 1.8 V domain I/O Ring Core Memories Standby circuitry digital (Wakeup logic, peripherals IWDG) Voltage Regulator Low voltage detector...
Page 69: Battery Backup Domain
Power control (PWR) RM0008 5.1.2 Battery backup domain To retain the content of the Backup registers and supply the RTC function when V turned off, V pin can be connected to an optional standby voltage supplied by a battery or by another source. The V pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 IOs, allowing the RTC to operate even when the main digital supply (V...
Page 70: Voltage Regulator
RM0008 Power control (PWR) 5.1.3 Voltage regulator The voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes. • In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories and digital peripherals).
Page 71: Figure 6. Pvd Thresholds
Power control (PWR) RM0008 PVD output interrupt can be generated when V drops below the PVD threshold and/or when V rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.
Page 72: Low-Power Modes
RM0008 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power Reset. Several low- power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event.
Page 73: Peripheral Clock Gating
Power control (PWR) RM0008 5.3.2 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 74: Stop Mode
RM0008 Power control (PWR) Table 12. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and Mode entry – SLEEPONEXIT = 0 ® Refer to the Cortex -M3 System Control register. If WFI was used for entry: Interrupt: Refer to Section 10.1.2: Interrupt and exception vectors on...
Page 75: Table 14. Stop Mode
Power control (PWR) RM0008 Section 19.3: IWDG functional description Section 19: Independent watchdog (IWDG). • real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
Page 76: Standby Mode
RM0008 Power control (PWR) 5.3.5 Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the ® Cortex -M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also switched off.
Page 77: Auto-Wakeup (Awu) From Low-Power Mode
Power control (PWR) RM0008 I/O states in Standby mode In Standby mode, all I/O pins are high impedance except: • Reset pad (still available) • TAMPER pin if configured for tamper or calibration out • WKUP pin, if enabled Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby ®...
Page 78 RM0008 Power control (PWR) Bits 31:9 Reserved, must be kept at reset value.. Bit 8 DBP: Disable backup domain write protection. In reset state, the RTC and backup registers are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC and Backup registers disabled 1: Access to RTC and Backup registers enabled Note: If the HSE divided by 128 is used as the RTC clock, this bit must remain set to 1.
Page 79: Power Control/Status Register (Pwr_Csr)
Power control (PWR) RM0008 5.4.2 Power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. Reserved EWUP PVDO Reserved Reserved Bits 31:9 Reserved, must be kept at reset value.
Page 80: Pwr Register Map
RM0008 Power control (PWR) 5.4.3 PWR register map The following table summarizes the PWR registers. Table 16. PWR register map and reset values Offset Register PWR_CR [2:0] 0x000 Reserved Reset value 0 0 0 0 0 0 0 0 0 PWR_CSR 0x004 Reserved...
Page 81: Backup Registers (Bkp)
Backup registers (BKP) RM0008 Backup registers (BKP) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 82: Bkp Functional Description
RM0008 Backup registers (BKP) BKP functional description 6.3.1 Tamper detection The TAMPER pin generates a Tamper detection event when the pin changes from 0 to 1 or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR).
Page 83: Bkp Registers
Backup registers (BKP) RM0008 BKP registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 6.4.1 Backup data register x (BKP_DRx) (x = 1 ..42) Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 D[15:0]...
Page 84: Backup Control Register (Bkp_Cr)
RM0008 Backup registers (BKP) Bit 8 ASOE: Alarm or second output enable Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit. The output pulse duration is one RTC clock period. The TAMPER pin must not be enabled while the ASOE bit is set.
Page 85: Bkp Register Map
Backup registers (BKP) RM0008 Bits 15:10 Reserved, must be kept at reset value. Bit 9 TIF: Tamper interrupt flag This bit is set by hardware when a Tamper event is detected and the TPIE bit is set. It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if the TPIE bit is reset.
Page 86 RM0008 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register BKP_DR2 D[15:0] 0x08 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value BKP_DR3 D[15:0] 0x0C Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value...
Page 87 Backup registers (BKP) RM0008 Table 17. BKP register map and reset values (continued) Offset Register BKP_DR12 D[15:0] 0x44 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value BKP_DR13 D[15:0] 0x48 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value...
Page 88 RM0008 Backup registers (BKP) Table 17. BKP register map and reset values (continued) Offset Register BKP_DR26 D[15:0] 0x7C Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value BKP_DR27 D[15:0] 0x80 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value...
Page 89 Backup registers (BKP) RM0008 Table 17. BKP register map and reset values (continued) Offset Register BKP_DR40 D[15:0] 0xB4 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0xB8 BKP_DR41 D[15:0] Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value...
Page 90: Low-, Medium-, High- And Xl-Density Reset And Clock Control (Rcc)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Low-, medium-, high- and XL-density reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
Page 91: Power Reset
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Low-power management reset There are two ways to generate a low-power management reset: Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
Page 92: Backup Domain Reset
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.1.3 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the Backup domain control register...
Page 93: Figure 8. Clock Tree
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Figure 8. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics”...
Page 94: Hse Clock
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) The timer clock frequencies are automatically fixed by hardware. There are two cases: if the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected.
Page 95: Hsi Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 96: Pll
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.2.3 The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock frequency. Refer to Figure 8 Clock control register (RCC_CR). The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL input clock, and multiplication factor) must be done before enabling the PLL.
Page 97: System Clock (Sysclk) Selection
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 LSI calibration The frequency dispersion of the Low Speed Internal RC (LSI) oscillator can be calibrated to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy.
Page 98: Rtc Clock
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.2.8 RTC clock The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
Page 99: Rcc Registers
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 RCC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. 7.3.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. Access: no wait state, word, half-word and byte access PLLON Reserved...
Page 100 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 16 HSEON: HSE clock enable Set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration...
Page 101: Clock Configuration Register (Rcc_Cfgr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.2 Clock configuration register (RCC_CFGR) Address offset: 0x04 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. MCO[2:0] PLLMUL[3:0] XTPRE...
Page 102 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bits 21:18 PLLMUL: PLL multiplication factor These bits are written by software to define the PLL multiplication factor. These bits can be written only when PLL is disabled. Caution: The PLL output frequency must not exceed 72 MHz. 0000: PLL input clock x 2 0001: PLL input clock x 3 0010: PLL input clock x 4...
Page 103 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bits 10:8 PPRE1: APB low-speed prescaler (APB1) Set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4...
Page 104: Clock Interrupt Register (Rcc_Cir)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.3 Clock interrupt register (RCC_CIR) Address offset: 0x08 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access CSSC RDYC RDYC RDYC RDYC RDYC Reserved Reserved CSSF RDYIE RDYIE...
Page 105 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 4-16 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization.
Page 106: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is set. Cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag...
Page 107 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 15 ADC3RST: ADC3 interface reset Set and cleared by software. 0: No effect 1: Reset ADC3 interface Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software.
Page 108 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset IO port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset IO port B Bit 2 IOPARST: IO port A reset...
Page 109: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.5 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access USART USART I2C2 I2C1 UART5 UART4 Reserved Res.
Page 110 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 20 UART5RST: USART5 reset Set and cleared by software. 0: No effect 1: Reset USART5 Bit 19 UART4RST: USART4 reset Set and cleared by software. 0: No effect 1: Reset USART4 Bit 18 USART3RST: USART3 reset Set and cleared by software.
Page 111: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 5 TIM7RST: TIM7 timer reset Set and cleared by software. 0: No effect 1: Reset TIM7 Bit 4 TIM6RST: TIM6 timer reset Set and cleared by software. 0: No effect 1: Reset TIM6 Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software.
Page 112: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 8 FSMCEN: FSMC clock enable Set and cleared by software. 0: FSMC clock disabled 1: FSMC clock enabled Bit 7 Reserved, always read as 0. Bit 6 CRCEN: CRC clock enable Set and cleared by software.
Page 113 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 TIM11 TIM10 TIM9 Reserved Reserved ADC3 TIM8 SPI1 TIM1 ADC2 ADC1 IOPG IOPF IOPE IOPD IOPC IOPB IOPA AFIO USART Res. Bits 31:22 Reserved, must be kept at reset value. Bit 21 TIM11EN: TIM11 timer clock enable Set and cleared by software.
Page 114 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 9 ADC1EN: ADC 1 interface clock enable Set and cleared by software. 0: ADC 1 interface disabled 1: ADC 1 interface clock enabled Bit 8 IOPGEN: IO port G clock enable Set and cleared by software.
Page 115: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going.
Page 116 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 22 I2C2EN: I2C2 clock enable Set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable Set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 UART5EN: USART5 clock enable...
Page 117 Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 7 TIM13EN: TIM13 timer clock enable Set and cleared by software. 0: TIM13 clock disabled 1: TIM13 clock enabled Bit 6 TIM12EN: TIM12 timer clock enable Set and cleared by software. 0: TIM12 clock disabled 1: TIM12 clock enabled Bit 5 TIM7EN: TIM7 timer clock enable...
Page 118: Backup Domain Control Register (Rcc_Bdcr)
RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) 7.3.9 Backup domain control register (RCC_BDCR) Address offset: 0x20 Reset value: 0x0000 0000, reset by Backup domain Reset. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 119: Control/Status Register (Rcc_Csr)
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 Bit 2 LSEBYP: External low-speed oscillator bypass Set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the external 32 kHz oscillator is disabled. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 1 LSERDY: External low-speed oscillator ready...
Page 120 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Bit 31 LPWRRSTF: Low-power reset flag Set by hardware when a Low-power management reset occurs. Cleared by writing to the RMVF bit. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Low-power management reset.
Page 121: Rcc Register Map
Low-, medium-, high- and XL-density reset and clock control (RCC) RM0008 7.3.11 RCC register map The following table gives the RCC register map and the reset values. Table 18. RCC register map and reset values Offset Register RCC_CR HSICAL[7:0] HSITRIM[4:0] 0x00 Reserved Reserved...
Page 122 RM0008 Low-, medium-, high- and XL-density reset and clock control (RCC) Table 18. RCC register map and reset values (continued) Offset Register RCC_CSR 0x24 Reserved 0 0 0 0 1 1 Reset value Refer to Table 1 on page 24 for the register boundary addresses.
Page 123: Connectivity Line Devices: Reset And Clock Control (Rcc)
Connectivity line devices: reset and clock control (RCC) RM0008 Connectivity line devices: reset and clock control (RCC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
Page 124: Power Reset
RM0008 Connectivity line devices: reset and clock control (RCC) Low-power management reset There are two ways to generate a low-power management reset: Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode.
Page 125: Backup Domain Reset
Connectivity line devices: reset and clock control (RCC) RM0008 8.1.3 Backup domain reset The backup domain has two specific resets that affect only the backup domain (see Figure A backup domain reset is generated when one of the following events occurs: Software reset, triggered by setting the BDRST bit in the Backup domain control register...
Page 126: Figure 11. Clock Tree
RM0008 Connectivity line devices: reset and clock control (RCC) Figure 11. Clock tree 40 kHz to independent watchdog IWDGCLK to RTC OSC32_IN 32.768 kHz RTCCLK OSC32_OUT /128 RTCSEL[1:0] FLITFCLK to Flash prog. IF XT1 to MCO 8 MHz SYSCLK HSI RC PLLMUL system clock 3-25 MHz...
Page 127: Hse Clock
Connectivity line devices: reset and clock control (RCC) RM0008 Several prescalers allow the configuration of the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the APB2 domains is 72 MHz. The maximum allowed frequency of the APB1 domain is 36 MHz.
Page 128: Hsi Clock
RM0008 Connectivity line devices: reset and clock control (RCC) Figure 12. HSE/ LSE clock sources Clock source Hardware configuration OSC_OUT External clock (HiZ) External source OSC_IN OSC_OUT Crystal/ceramicr esonators Load capacitors External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 50 MHz.
Page 129: Plls
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at T = 25 °C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 130: Lsi Clock
RM0008 Connectivity line devices: reset and clock control (RCC) External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain control register (RCC_BDCR).
Page 131: Clock Security System (Css)
Connectivity line devices: reset and clock control (RCC) RM0008 8.2.7 Clock security system (CSS) Clock Security System can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. a failure is detected on the HSE clock, the HSE Oscillator is automatically disabled, a clock failure event is sent to the break input of the TIM1 Advanced control timer and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt CSSI),...
Page 132: Clock-Out Capability
RM0008 Connectivity line devices: reset and clock control (RCC) 8.2.10 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 8 clock signals can be selected as the MCO clock.
Page 133 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 27 PLL2RDY: PLL2 clock ready flag Set by hardware to indicate that the PLL2 is locked. 0: PLL2 unlocked 1: PLL2 locked Bit 26 PLL2ON: PLL2 enable Set and cleared by software to enable PLL2. Cleared by hardware when entering Stop or Standby mode.
Page 134: Clock Configuration Register (Rcc_Cfgr)
RM0008 Connectivity line devices: reset and clock control (RCC) Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming These bits provide an additional user-programmable trimming value that is added to the HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that influence the frequency of the internal HSI RC.
Page 135 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 31:27 Reserved, must be kept at reset value. Bits 26:24 MCO[3:0]: Microcontroller clock output Set and cleared by software. 00xx: No clock 0100: System clock (SYSCLK) selected 0101: HSI clock selected 0110: HSE clock selected 0111: PLL clock divided by 2 selected 1000: PLL2 clock selected...
Page 136 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 16 PLLSRC: PLL entry clock source Set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI oscillator clock / 2 selected as PLL input clock 1: Clock from PREDIV1 selected as PLL input clock Note: When changing the main PLL’s entry clock source, the original clock source must be switched off only after the selection of the new clock source.
Page 137: Clock Interrupt Register (Rcc_Cir)
Connectivity line devices: reset and clock control (RCC) RM0008 Bits 7:4 HPRE[3:0]: AHB prescaler Set and cleared by software to control AHB clock division factor. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128...
Page 138 RM0008 Connectivity line devices: reset and clock control (RCC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 CSSC: Clock security system interrupt clear This bit is set by software to clear the CSSF flag. 0: No effect 1: Clear CSSF flag Bit 22 PLL3RDYC: PLL3 Ready Interrupt Clear This bit is set by software to clear the PLL3RDYF flag.
Page 139 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 11 HSERDYIE: HSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the external 3-25 MHz oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 10 HSIRDYIE: HSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the internal 8 MHz RC oscillator stabilization.
Page 140 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 2 HSIRDYF: HSI ready interrupt flag Set by hardware when the Internal High Speed clock becomes stable and HSIRDYIE is set. It is cleared by software setting the HSIRDYC bit. 0: No clock ready interrupt caused by the internal 8 MHz RC oscillator 1: Clock ready interrupt caused by the internal 8 MHz RC oscillator Bit 1 LSERDYF: LSE ready interrupt flag...
Page 141: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
Connectivity line devices: reset and clock control (RCC) RM0008 8.3.4 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x0C Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access Reserved USART1 SPI1 TIM1 ADC2 ADC1 IOPE IOPD IOPC IOPB IOPA AFIO...
Page 142: Apb1 Peripheral Reset Register (Rcc_Apb1Rstr)
RM0008 Connectivity line devices: reset and clock control (RCC) Bit 4 IOPCRST: IO port C reset Set and cleared by software. 0: No effect 1: Reset I/O port C Bit 3 IOPBRST: IO port B reset Set and cleared by software. 0: No effect 1: Reset I/O port B Bit 2 IOPARST: I/O port A reset...
Page 143 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 26 CAN2RST: CAN2 reset Set and cleared by software. 0: No effect 1: Reset CAN2 Bit 25 CAN1RST: CAN1 reset Set and cleared by software. 0: No effect 1: Reset CAN1 Bits 24:23 Reserved, must be kept at reset value.
Page 144 RM0008 Connectivity line devices: reset and clock control (RCC) Bit 11 WWDGRST: Window watchdog reset Set and cleared by software. 0: No effect 1: Reset window watchdog Bits 10:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software.
Page 145: Ahb Peripheral Clock Enable Register (Rcc_Ahbenr)
Connectivity line devices: reset and clock control (RCC) RM0008 8.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) Address offset: 0x14 Reset value: 0x0000 0014 Access: no wait state, word, half-word and byte access MACRX Reserved ETHM ETHM OTGFS SRAM DMA2 DMA1 FLITFE ACTXE CRCEN...
Page 146: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
RM0008 Connectivity line devices: reset and clock control (RCC) Bit 4 FLITFEN: FLITF clock enable Set and cleared by software to disable/enable FLITF clock during sleep mode. 0: FLITF clock disabled during Sleep mode 1: FLITF clock enabled during Sleep mode Bit 3 Reserved, must be kept at reset value.
Page 147 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 11 TIM1EN: TIM1 Timer clock enable Set and cleared by software. 0: TIM1 timer clock disabled 1: TIM1 timer clock enabled Bit 10 ADC2EN: ADC 2 interface clock enable Set and cleared by software. 0: ADC 2 interface clock disabled 1: ADC 2 interface clock enabled Bit 9 ADC1EN: ADC 1 interface clock enable...
Page 148: Apb1 Peripheral Clock Enable Register (Rcc_Apb1Enr)
RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.8 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x1C Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going.
Page 149 Connectivity line devices: reset and clock control (RCC) RM0008 Bit 21 I2C1EN: I2C 1 clock enable Set and cleared by software. 0: I2C 1 clock disabled 1: I2C 1 clock enabled Bit 20 UART5EN: USART 5 clock enable Set and cleared by software. 0: USART 5 clock disabled 1: USART 5 clock enabled Bit 19 UART4EN: USART 4 clock enable...
Page 150: Backup Domain Control Register (Rcc_Bdcr)
RM0008 Connectivity line devices: reset and clock control (RCC) Bit 3 TIM5EN: Timer 5 clock enable Set and cleared by software. 0: Timer 5 clock disabled 1: Timer 5 clock enabled Bit 2 TIM4EN: Timer 4 clock enable Set and cleared by software. 0: Timer 4 clock disabled 1: Timer 4 clock enabled Bit 1 TIM3EN: Timer 3 clock enable...
Page 151 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 31:17 Reserved, must be kept at reset value. Bit 16 BDRST: Backup domain software reset Set and cleared by software. 0: Reset not activated 1: Resets the entire Backup domain Bit 15 RTCEN: RTC clock enable Set and cleared by software.
Page 152: Control/Status Register (Rcc_Csr)
RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.10 Control/status register (RCC_CSR) Address: 0x24 Reset value: 0x0C00 0000, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in the case of successive accesses to this register.
Page 153: Ahb Peripheral Clock Reset Register (Rcc_Ahbrstr)
Connectivity line devices: reset and clock control (RCC) RM0008 Bit 24 RMVF: Remove reset flag Set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 23:2 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low speed oscillator ready Set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is stable.
Page 154: Clock Configuration Register2 (Rcc_Cfgr2)
RM0008 Connectivity line devices: reset and clock control (RCC) 8.3.12 Clock configuration register2 (RCC_CFGR2) Address offset: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access I2S3SR I2S2SR PREDIV 1SRC Reserved PLL2MUL[3:0] PLL3MUL[3:0] PREDIV2[3:0] PREDIV1[3:0] Bits 31:19 Reserved, must be kept at reset value. Bit 18 I2S3SRC: I2S3 clock source Set and cleared by software to select I2S3 clock source.
Page 155 Connectivity line devices: reset and clock control (RCC) RM0008 Bits 11:8 PLL2MUL[3:0]: PLL2 Multiplication Factor Set and cleared by software to control PLL2 multiplication factor. These bits can be written only when PLL2 is disabled. 00xx: Reserved 010x: Reserved 0110: PLL2 clock entry x 8 0111: PLL2 clock entry x 9 1000: PLL2 clock entry x 10 1001: PLL2 clock entry x 11...
Page 156: Rcc Register Map
RM0008 Connectivity line devices: reset and clock control (RCC) Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor Set and cleared by software to select PREDIV1 division factor. These bits can be written only when PLL is disabled. Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the RCC_CFGR register changes Bit(0) accordingly.
Page 157 Connectivity line devices: reset and clock control (RCC) RM0008 Table 19. RCC register map and reset values (continued) Offset Register RCC_APB2RSTR 0x00C Reserved 0 0 0 0 0 0 0 0 0 Reset value RCC_APB1RSTR Rese 0x010 Reserved rved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value...
Page 158 RM0008 Connectivity line devices: reset and clock control (RCC) Table 19. RCC register map and reset values (continued) Offset Register PLL3MUL PLL2MUL PREDIV2[3: PREDIV1[3: RCC_CFGR2 [3:0] [3:0] 0x02C Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Refer to Table 3 on page 51...
Page 159: General-Purpose And Alternate-Function I/Os (Gpios And Afios)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
Page 160: Figure 13. Basic Structure Of A Standard I/O Port Bit
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Figure 13. Basic structure of a standard I/O port bit Analog Input To on-chip peripheral on/off Alternate Function Input on/off Read TTL Schmitt Protection trigger on/off diode Input driver I/O pin Write Output driver Protection diode...
Page 161: General-Purpose I/O (Gpio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 20. Port bit configuration table PxODR Configuration mode CNF1 CNF0 MODE1 MODE0 register Push-pull 0 or 1 General purpose output Open-drain 0 or 1 Push-pull don’t care Alternate Function Table 21 output Open-drain don’t care...
Page 162: External Interrupt/Wakeup Lines
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) or for reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be modified. 9.1.3 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.
Page 163: Input Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.1.7 Input configuration When the I/O Port is programmed as Input: • The Output Buffer is disabled • The Schmitt Trigger Input is activated • The weak pull-up and pull-down resistors are activated or not depending on input configuration (pull-up, pull-down or floating): •...
Page 164: Output Configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.1.8 Output configuration When the I/O Port is programmed as Output: • The Output Buffer is enabled: – Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in the Output register leaves the port in Hi-Z.
Page 165: Alternate Function Configuration
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.1.9 Alternate function configuration When the I/O Port is programmed as Alternate Function: • The Output Buffer is turned on in Open Drain or Push-Pull configuration • The Output Buffer is driven by the signal coming from the peripheral (alternate function out) •...
Page 166: Analog Configuration
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.1.10 Analog configuration When the I/O Port is programmed as Analog configuration: • The Output Buffer is disabled. • The Schmitt Trigger Input is de-activated providing zero consumption for every analog value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0). •...
Page 167: Table 23. General-Purpose Timers Tim2/3/4/5
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 23. General-purpose timers TIM2/3/4/5 TIM2/3/4/5 pinout Configuration GPIO configuration Input capture channel x Input floating TIM2/3/4/5_CHx Output compare channel x Alternate function push-pull TIM2/3/4/5_ETR External trigger timer input Input floating Table 24. USARTs USART pinout Configuration GPIO configuration...
Page 168: Table 26. I2S
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 26. I2S I2S pinout Configuration GPIO configuration Master Alternate function push-pull I2Sx_ WS Slave Input floating Master Alternate function push-pull I2Sx_CK Slave Input floating Transmitter Alternate function push-pull I2Sx_SD Receiver Input floating/ Input pull-up/ Input pull-down Master Alternate function push-pull I2Sx_MCK...
Page 169: Table 31. Sdio
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 30. OTG_FS pin configuration OTG_FS pinout Configuration GPIO configuration No need if the Force host mode is selected by software Host (FHMOD set in the OTG_FS_GUSBCFG register) OTG_FS_ID No need if the Force device mode is selected by software Device (FDMOD set in the OTG_FS_GUSBCFG register) Input pull-up...
Page 170: Table 33. Other Ios
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 32. FSMC (continued) FSMC pinout GPIO configuration FSMC_NWAIT Input floating/ Input pull-up FSMC_CD FSMC_NIOS16, FSMC_INTR Input floating FSMC_INT[3:2] FSMC_NL Alternate function push-pull FSMC_NBL[1:0] FSMC_NIORD, FSMC_NIOWR Alternate function push-pull FSMC_NREG Table 33. Other IOs Pins Alternate function GPIO configuration...
Page 171: Gpio Registers
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 GPIO registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 9.2.1 Port configuration register low (GPIOx_CRL) (x=A..G) Address offset: 0x00 Reset value: 0x4444 4444 CNF7[1:0]...
Page 172: Port Configuration Register High (Gpiox_Crh) (X=A..g
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.2.2 Port configuration register high (GPIOx_CRH) (x=A..G) Address offset: 0x04 Reset value: 0x4444 4444 CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0] CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0] Bits 31:30, 27:26, CNFy[1:0]: Port x configuration bits (y= 8 ..
Page 173: Port Output Data Register (Gpiox_Odr) (X=A
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.2.4 Port output data register (GPIOx_ODR) (x=A..G) Address offset: 0x0C Reset value: 0x0000 0000 Reserved ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Bits 31:16 Reserved, must be kept at reset value.
Page 174: Port Bit Reset Register (Gpiox_Brr) (X=A
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.2.6 Port bit reset register (GPIOx_BRR) (x=A..G) Address offset: 0x14 Reset value: 0x0000 0000 Reserved BR15 BR14 BR13 BR12 BR11 BR10 Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0 .. 15) These bits are write-only and can be accessed in Word mode only.
Page 175: Alternate Function I/O And Debug Configuration (Afio)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 31:17 Reserved Bit 16 LCKK[16]: Lock key This bit can be read anytime. It can only be modified using the Lock Key Writing Sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 176: Can1 Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.3.3 CAN1 alternate function remapping The CAN signals can be mapped on Port A, Port B or Port D as shown in Table 34. For port D, remapping is not possible in devices delivered in 36-, 48- and 64-pin packages. Table 34.
Page 177: Adc Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 To optimize the number of free GPIOs during debugging, this mapping can be configured in different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O configuration register (AFIO_MAPR). Refer to Table 37 Table 37.
Page 178: Timer Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 41. ADC2 external trigger regular conversion alternate function remapping Alternate function ADC2_ETRGREG_REG = 0 ADC2_ETRGREG_REG = 1 ADC2 external trigger regular ADC2 external trigger regular ADC2 external trigger regular conversion is connected to conversion is connected to conversion EXTI11...
Page 179: Table 45. Tim2 Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 45. TIM2 alternate function remapping TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: Alternate function 0] = “00” (no 0] = “01” (partial 0] = “10” (partial 0] = “11” (full remap) remap) remap) remap) TIM2_CH1_ETR PA15 PA15...
Page 180: Usart Alternate Function Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 49. TIM11 remapping Alternate function TIM11_REMAP = 0 TIM11_REMAP = 1 TIM11_CH1 1. Refer to the AF remap and debug I/O configuration register Section 9.4.7: AF remap and debug I/O configuration register2 (AFIO_MAPR2).
Page 181: I2C1 Alternate Function Remapping
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 54. USART1 remapping Alternate function USART1_REMAP = 0 USART1_REMAP = 1 USART1_TX USART1_RX PA10 9.3.9 I2C1 alternate function remapping Refer to AF remap and debug I/O configuration register (AFIO_MAPR) Table 55. I2C1 remapping Alternate function I2C1_REMAP = 0 I2C1_REMAP = 1...
Page 182: Table 58. Eth Remapping
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Table 58. ETH remapping Alternate function ETH_REMAP = 0 ETH_REMAP = 1 RX_DV-CRS_DV RXD0 RXD1 PD10 RXD2 PD11 RXD3 PD12 DocID13902 Rev 15 182/1128...
Page 183: Afio Registers
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 AFIO registers Refer to Section 2.1 on page 47for a list of abbreviations used in register descriptions. Note: To read/write the AFIO_EVCR, AFIO_MAPR and AFIO_EXTICRX registers, the AFIO clock should first be enabled. Refer to Section 7.3.7: APB2 peripheral clock enable register (RCC_APB2ENR).
Page 184: Af Remap And Debug I/O Configuration Register (Afio_Mapr)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.4.2 AF remap and debug I/O configuration register (AFIO_MAPR) Address offset: 0x04 Reset value: 0x0000 0000 Memory map and bit definitions for low-, medium- high- and XL-density devices: ADC2_ ADC1_E ADC1_ ADC2_E TIM5C SWJ_ ETRG...
Page 185 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 17 ADC1_ETRGINJ_REMAP: ADC 1 External trigger injected conversion remapping Set and cleared by software. This bit controls the trigger input connected to ADC1 External trigger injected conversion. When reset the ADC1 External trigger injected conversion is connected to EXTI15.
Page 186 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bits 7:6 TIM1_REMAP[1:0]: TIM1 remapping These bits are set and cleared by software. They control the mapping of TIM1 channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on the GPIO ports. 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6,...
Page 187 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Memory map and bit definitions for connectivity line devices: TIM2IT PTP_P SPI3_ MII_R CAN2_ TIM5C SWJ_ ETH_R PS_RE REMA MII_SE REMA H4_IRE IREMA CFG[2:0] EMAP Res. Res. Reserved PD01_ TIM4_ USART2 USART1 I2C1_ SPI1_ CAN1_REMAP...
Page 188 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 23 MII_RMII_SEL: MII or RMII selection This bit is set and cleared by software. It configures the Ethernet MAC internally for use with an external MII or RMII PHY. 0: Configure Ethernet MAC for connection with an MII PHY 1: Configure Ethernet MAC for connection with an RMII PHY Note: This bit is available only in connectivity line devices and is reserved otherwise.
Page 189 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Bits 11:10 TIM3_REMAP[1:0]: TIM3 remapping These bits are set and cleared by software. They control the mapping of TIM3 channels 1 to 4 on the GPIO ports. 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01: Not used 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Page 190 RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) Bit 2 USART1_REMAP: USART1 remapping This bit is set and cleared by software. It controls the mapping of USART1 TX and RX alternate functions on the GPIO ports. 0: No remap (TX/PA9, RX/PA10) 1: Remap (TX/PB6, RX/PB7) Bit 1 I2C1_REMAP: I2C1 remapping This bit is set and cleared by software.
Page 191: External Interrupt Configuration Register 1 (Afio_Exticr1)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.3 External interrupt configuration register 1 (AFIO_EXTICR1) Address offset: 0x08 Reset value: 0x0000 Reserved EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 0 to 3) These bits are written by software to select the source input for EXTIx external interrupt. Refer to Section 10.2.5: External interrupt/event line mapping on page 208 0000: PA[x] pin...
Page 192: External Interrupt Configuration Register 3 (Afio_Exticr3)
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) 9.4.5 External interrupt configuration register 3 (AFIO_EXTICR3) Address offset: 0x10 Reset value: 0x0000 Reserved EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0] Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x= 8 to 11) These bits are written by software to select the source input for EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin...
Page 193: Af Remap And Debug I/O Configuration Register2 (Afio_Mapr2)
General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 9.4.7 AF remap and debug I/O configuration register2 (AFIO_MAPR2) Address offset: 0x1C Reset value: 0x0000 0000 Reserved TIM14_ TIM13_ TIM11_ TIM10_ TIM9_ C_NA REMA REMA REMA REMA REMA Reserved Reserved Bits 31:11 Reserved.
Page 194: Gpio And Afio Register Maps
RM0008 General-purpose and alternate-function I/Os (GPIOs and AFIOs) GPIO and AFIO register maps Refer to Table 3 on page 51 for the register boundary addresses. The following tables give the GPIO and AFIO register map and the reset values. Table 59. GPIO register map and reset values Offset Register MODE...
Page 195 General-purpose and alternate-function I/Os (GPIOs and AFIOs) RM0008 Table 60. AFIO register map and reset values (continued) Offset Register AFIO_MAPR connectivity line 0x04 devices Reset value SWJ_ AFIO_MAPR CFG[2:0] 0x04 Reserved Reserved Reset value AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0] 0x08 Reserved Reset value AFIO_EXTICR2...
Page 196: Interrupts And Events
RM0008 Interrupts and events Interrupts and events Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 197: Interrupt And Exception Vectors
Interrupts and events RM0008 10.1.2 Interrupt and exception vectors Table 61 Table 63 are the vector tables for connectivity line and other STM32F10xxx devices, respectively. Table 61. Vector table for connectivity line devices Type of Acronym Description Address priority Reserved 0x0000_0000 fixed Reset...
Page 198 RM0008 Interrupts and events Table 61. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority settable EXTI4 EXTI Line4 interrupt 0x0000_0068 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_006C settable DMA1_Channel2 DMA1 Channel2 global interrupt 0x0000_0070 settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074...
Page 199 Interrupts and events RM0008 Table 61. Vector table for connectivity line devices (continued) Type of Acronym Description Address priority settable USART3 USART3 global interrupt 0x0000_00DC settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0 RTC alarm through EXTI line settable RTCAlarm 0x0000_00E4 interrupt USB On-The-Go FS Wakeup settable OTG_FS_WKUP...
Page 200: Table 62. Vector Table For Xl-Density Devices
RM0008 Interrupts and events Table 62. Vector table for XL-density devices Type of Acronym Description Address priority Reserved 0x0000_0000 -3 fixed Reset Reset 0x0000_0004 Nonmaskable interrupt. The RCC -2 fixed Clock Security System (CSS) is 0x0000_0008 linked to the NMI vector. -1 fixed HardFault All class of fault...
Page 201 Interrupts and events RM0008 Table 62. Vector table for XL-density devices (continued) Type of Acronym Description Address priority 14 21 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078 15 22 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C 16 23 settable DMA1_Channel6 DMA1 Channel6 global interrupt 0x0000_0080 17 24 settable DMA1_Channel7...
Page 202 RM0008 Interrupts and events Table 62. Vector table for XL-density devices (continued) Type of Acronym Description Address priority RTC alarm through EXTI line 41 48 settable RTCAlarm 0x0000_00E4 interrupt USB wakeup from suspend through 42 49 settable USBWakeUp 0x0000_00E8 EXTI line interrupt TIM8 Break interrupt and TIM12 43 50 settable TIM8_BRK_TIM12 0x0000_00EC...
Page 203: Table 63. Vector Table For Other Stm32F10Xxx Devices
Interrupts and events RM0008 Table 63. Vector table for other STM32F10xxx devices Type of Acronym Description Address priority Reserved 0x0000_0000 fixed Reset Reset 0x0000_0004 Non maskable interrupt. The RCC fixed Clock Security System (CSS) is 0x0000_0008 linked to the NMI vector. fixed HardFault All class of fault...
Page 204 RM0008 Interrupts and events Table 63. Vector table for other STM32F10xxx devices (continued) Type of Acronym Description Address priority settable DMA1_Channel3 DMA1 Channel3 global interrupt 0x0000_0074 settable DMA1_Channel4 DMA1 Channel4 global interrupt 0x0000_0078 settable DMA1_Channel5 DMA1 Channel5 global interrupt 0x0000_007C settable DMA1_Channel6 DMA1 Channel6 global interrupt...
Page 205: External Interrupt/Event Controller (Exti)
Interrupts and events RM0008 Table 63. Vector table for other STM32F10xxx devices (continued) Type of Acronym Description Address priority RTC alarm through EXTI line settable RTCAlarm 0x0000_00E4 interrupt USB wakeup from suspend through settable USBWakeup 0x0000_00E8 EXTI line interrupt settable TIM8_BRK TIM8 Break interrupt 0x0000_00EC...
Page 206: Main Features
RM0008 Interrupts and events 10.2.1 Main features The EXTI controller main features are the following: • Independent trigger and mask on each interrupt/event line • Dedicated status bit for each interrupt line • Generation of up to 20 software event/interrupt requests •...
Page 207: Functional Description
Interrupts and events RM0008 resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. • or configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.
Page 208: External Interrupt/Event Line Mapping
RM0008 Interrupts and events 10.2.5 External interrupt/event line mapping The 112 GPIOs are connected to the 16 external interrupt/event lines in the following manner: Figure 21. External interrupt/event GPIO mapping EXTI0[3:0] bits in AFIO_EXTICR1 register EXTI0 EXTI1[3:0] bits in AFIO_EXTICR1 register EXTI1 EXTI15[3:0] bits in AFIO_EXTICR4 register PA15...
Page 209 Interrupts and events RM0008 The four other EXTI lines are connected as follows: • EXTI line 16 is connected to the PVD output • EXTI line 17 is connected to the RTC Alarm event • EXTI line 18 is connected to the USB Wakeup event •...
Page 210: Exti Registers
RM0008 Interrupts and events 10.3 registers EXTI Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 MR19 MR18...
Page 211: Rising Trigger Selection Register (Exti_Rtsr)
Interrupts and events RM0008 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 TR19 TR18 TR17 TR16 Reserved TR15 TR14 TR13 TR12 TR11 TR10 Bits 31:20 Reserved, must be kept at reset value (0). Bits 19:0 TRx: Rising trigger event configuration bit of line x 0: Rising trigger disabled (for Event and Interrupt) for input line 1: Rising trigger enabled (for Event and Interrupt) for input line.
Page 212: Software Interrupt Event Register (Exti_Swier)
RM0008 Interrupts and events 10.3.5 Software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 SWIER SWIER SWIER SWIER Reserved SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER Bits 31:20 Reserved, must be kept at reset value (0).
Page 213: Exti Register Map
Interrupts and events RM0008 10.3.7 EXTI register map The following table gives the EXTI register map and the reset values. Bits 19 in all registers, are used in connectivity line devices and is reserved otherwise. Table 64. External interrupt/event controller register map and reset values Offset Register MR[19:0]...
Page 214: Analog-To-Digital Converter (Adc)
RM0008 Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 215: Adc Main Features
Analog-to-digital converter (ADC) RM0008 11.2 ADC main features • 12-bit resolution • Interrupt generation at End of Conversion, End of Injected conversion and Analog watchdog event • Single and continuous conversion modes • Scan mode for automatic conversion of channel 0 to channel ‘n’ •...
Page 216: Figure 22. Single Adc Block Diagram
RM0008 Analog-to-digital converter (ADC) Figure 22. Single ADC block diagram Interrupt Flags enable bits End of conversion EOCIE ADC Interrupt to NVIC End of injected conversion JEOC JEOCIE Analog watchdog event AWDIE Analog watchdog Compare Result High Threshold (12 bits) Low Threshold (12 bits) Injected data registers REF+...
Page 217: Table 65. Adc Pins
Analog-to-digital converter (ADC) RM0008 Table 65. ADC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the ADC, REF+ ≤ ≤ positive 2.4 V REF+ Analog power supply equal to V Input, analog supply ≤ ≤ 2.4 V 3.6 V Input, analog reference...
Page 218: Adc On-Off Control
RM0008 Analog-to-digital converter (ADC) 11.3.1 ADC on-off control The ADC can be powered-on by setting the ADON bit in the ADC_CR2 register. When the ADON bit is set for the first time, it wakes up the ADC from Power Down mode. Conversion starts when ADON bit is set for a second time by software after ADC power-up time (t STAB...
Page 219: Continuous Conversion Mode
Analog-to-digital converter (ADC) RM0008 Once the conversion of the selected channel is complete: • If a regular channel was converted: – The converted data is stored in the 16-bit ADC_DR register – The EOC (End Of Conversion) flag is set –...
Page 220: Analog Watchdog
RM0008 Analog-to-digital converter (ADC) 11.3.7 Analog watchdog The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by using the AWDIE bit in the ADC_CR1 register.
Page 221: Injected Channel Management
Analog-to-digital converter (ADC) RM0008 11.3.9 Injected channel management Triggered injection To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the ADC_CR1 register. Start conversion of a group of regular channels either by external trigger or by setting the ADON bit in the ADC_CR2 register.
Page 222: Discontinuous Mode
RM0008 Analog-to-digital converter (ADC) 11.3.10 Discontinuous mode Regular group This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to convert a short sequence of n conversions (n <=8) which is a part of the sequence of conversions selected in the ADC_SQRx registers.
Page 223: Data Alignment
Analog-to-digital converter (ADC) RM0008 (digital word) is calculated for each capacitor, and during all subsequent conversions, the error contribution of each capacitor is removed using this code. Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is over, the CAL bit is reset by hardware and normal conversion can be performed.
Page 224: Channel-By-Channel Programmable Sample Time
RM0008 Analog-to-digital converter (ADC) 11.6 Channel-by-channel programmable sample time ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us- ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled with a different sample time. The total conversion time is calculated as follows: Tconv = Sampling time + 12.5 cycles Example:...
Page 225: Table 68. External Trigger For Injected Channels For Adc1 And Adc2
Analog-to-digital converter (ADC) RM0008 Table 68. External trigger for injected channels for ADC1 and ADC2 Source Connection type JEXTSEL[2:0] TIM1_TRGO event TIM1_CC4 event TIM2_TRGO event Internal signal from on-chip timers TIM2_CC1 event TIM3_CC4 event TIM4_TRGO event EXTI line 15/TIM8_CC4 External pin/Internal signal from (1)(2) event on-chip timers...
Page 226: Dma Request
RM0008 Analog-to-digital converter (ADC) The software source trigger events can be generated by setting a bit in a register (SWSTART and JSWSTART in ADC_CR2). A regular group conversion can be interrupted by an injected trigger. 11.8 DMA request Since converted regular channels value are stored in a unique data register, it is necessary to use DMA for conversion of more than one regular channel.
Page 227: Dual Adc Mode
Analog-to-digital converter (ADC) RM0008 11.9 Dual ADC mode In devices with two ADCs or more, dual ADC mode can be used (see Figure 29). In dual ADC mode the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0] bits in the ADC1_CR1 register.
Page 228: Figure 29. Dual Adc Block Diagram
RM0008 Analog-to-digital converter (ADC) Figure 29. Dual ADC block diagram Regular data register (12 bits) (16 bits) Injected data registers (4 x 16 bits) Regular ADC2 (Slave) channels injected channels internal triggers Regular data register (16 bits) Injected data registers (4 x 16 bits) ADCx_IN0 Regular...
Page 229: Injected Simultaneous Mode
Analog-to-digital converter (ADC) RM0008 11.9.1 Injected simultaneous mode This mode converts an injected channel group. The source of external trigger comes from the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits ADC1_CR2 in the register). A simultaneous trigger is provided to ADC2. Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the two ADCs when converting the same channel).
Page 230: Fast Interleaved Mode
RM0008 Analog-to-digital converter (ADC) Figure 31. Regular simultaneous mode on 16 channels Sampling Conversion ADC1 CH15 ADC2 CH15 CH14 CH13 CH12 End of conversion on ADC1 and ADC2 Trigger 11.9.3 Fast interleaved mode This mode can be started only on a regular channel group (usually one channel). The source of external trigger comes from the regular channel mux of ADC1.
Page 231: Alternate Trigger Mode
Analog-to-digital converter (ADC) RM0008 After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the ADC1 converted data in the lower halfword.
Page 232: Independent Mode
RM0008 Analog-to-digital converter (ADC) If the injected discontinuous mode is enabled for both ADC1 and ADC2: • When the 1st trigger occurs, the first injected channel in ADC1 is converted. • When the 2nd trigger arrives, the first injected channel in ADC2 are converted •...
Page 233: Combined Injected Simultaneous + Interleaved
Analog-to-digital converter (ADC) RM0008 Figure 36. Alternate + Regular simultaneous 1st trig ADC1 reg ADC1 inj ADC2 reg ADC2 inj synchro not lost 2nd trig If a trigger occurs during an injected conversion that has interrupted a regular conversion, it will be ignored.
Page 234: Temperature Sensor
RM0008 Analog-to-digital converter (ADC) 11.10 Temperature sensor The temperature sensor can be used to measure the ambient temperature (T ) of the device. The temperature sensor is internally connected to the ADCx_IN16 input channel which is used to convert the sensor output voltage into a digital value. The recommended sampling time for the temperature sensor is 17.1 µs.
Page 235: Adc Interrupts
Analog-to-digital converter (ADC) RM0008 Reading the temperature To use the sensor: Select the ADCx_IN16 input channel. Select a sample time of 17.1 µs Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake up the temperature sensor from power down mode. Start the ADC conversion by setting the ADON bit (or by external trigger).
Page 236: Adc Registers
RM0008 Analog-to-digital converter (ADC) 11.12 ADC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 11.12.1 ADC status register (ADC_SR) Address offset: 0x00 Reset value: 0x0000 0000 Reserved STRT...
Page 237: Adc Control Register 1 (Adc_Cr1)
Analog-to-digital converter (ADC) RM0008 11.12.2 ADC control register 1 (ADC_CR1) Address offset: 0x04 Reset value: 0x0000 0000 AWDE JAWDE DUALMOD[3:0] Reserved Reserved JDISCE DISC JEOC DISCNUM[2:0] JAUTO SCAN AWDIE EOCIE AWDCH[4:0] Bits 31:24 Reserved, must be kept at reset value. Bit 23 AWDEN: Analog watchdog enable on regular channels This bit is set/reset by software.
Page 238 RM0008 Analog-to-digital converter (ADC) Bit 12 JDISCEN: Discontinuous mode on injected channels This bit set and cleared by software to enable/disable discontinuous mode on injected group channels 0: Discontinuous mode on injected channels disabled 1: Discontinuous mode on injected channels enabled Bit 11 DISCEN: Discontinuous mode on regular channels This bit set and cleared by software to enable/disable Discontinuous mode on regular channels.
Page 239: Adc Control Register 2 (Adc_Cr2)
Analog-to-digital converter (ADC) RM0008 Bit 6 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Bit 5 EOCIE: Interrupt enable for EOC This bit is set and cleared by software to enable/disable the End of Conversion interrupt.
Page 240 RM0008 Analog-to-digital converter (ADC) Bits 31:24 Reserved, must be kept at reset value. Bit 23 TSVREFE: Temperature sensor and V enable REFINT This bit is set and cleared by software to enable/disable the temperature sensor and V REFINT channel. In devices with dual ADCs this bit is present only in ADC1. 0: Temperature sensor and V channel disabled REFINT...
Page 241 Analog-to-digital converter (ADC) RM0008 Bit 15 JEXTTRIG: External trigger conversion mode for injected channels This bit is set and cleared by software to enable/disable the external trigger used to start conversion of an injected channel group. 0: Conversion on external event disabled 1: Conversion on external event enabled Bits 14:12 JEXTSEL[2:0]: External event select for injected group These bits select the external event used to trigger the start of conversion of an injected...
Page 242 RM0008 Analog-to-digital converter (ADC) Bit 2 CAL: A/D Calibration This bit is set by software to start the calibration. It is reset by hardware after calibration is complete. 0: Calibration completed 1: Enable calibration Bit 1 CONT: Continuous conversion This bit is set and cleared by software. If set conversion takes place continuously till this bit is reset.
Page 243: Adc Sample Time Register 1 (Adc_Smpr1)
Analog-to-digital converter (ADC) RM0008 11.12.4 ADC sample time register 1 (ADC_SMPR1) Address offset: 0x0C Reset value: 0x0000 0000 SMP17[2:0] SMP16[2:0] SMP15[2:1] Reserved SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] 15_0 Bits 31:24 Reserved, must be kept at reset value. Bits 23:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel.
Page 244: Adc Sample Time Register 2 (Adc_Smpr2)
RM0008 Analog-to-digital converter (ADC) 11.12.5 ADC sample time register 2 (ADC_SMPR2) Address offset: 0x10 Reset value: 0x0000 0000 Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1] Res. SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x Sample time selection These bits are written by software to select the sample time individually for each channel.
Page 245: Adc Watchdog High Threshold Register (Adc_Htr)
Analog-to-digital converter (ADC) RM0008 11.12.7 ADC watchdog high threshold register (ADC_HTR) Address offset: 0x24 Reset value: 0x0000 0FFF Reserved HT[11:0] Reserved Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 HT[11:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog. 11.12.8 ADC watchdog low threshold register (ADC_LTR) Address offset: 0x28...
Page 246: Adc Regular Sequence Register 1 (Adc_Sqr1)
RM0008 Analog-to-digital converter (ADC) 11.12.9 ADC regular sequence register 1 (ADC_SQR1) Address offset: 0x2C Reset value: 0x0000 0000 SQ16[4:1] L[3:0] Reserved SQ16_0 SQ15[4:0] SQ14[4:0] SQ13[4:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 L[3:0]: Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence.
Page 247: Adc Regular Sequence Register 2 (Adc_Sqr2)
Analog-to-digital converter (ADC) RM0008 11.12.10 ADC regular sequence register 2 (ADC_SQR2) Address offset: 0x30 Reset value: 0x0000 0000 SQ12[4:0] SQ11[4:0] SQ10[4:1] Reserved SQ10_ SQ9[4:0] SQ8[4:0] SQ7[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 12th in the sequence to be converted.
Page 248: Adc Regular Sequence Register 3 (Adc_Sqr3)
RM0008 Analog-to-digital converter (ADC) 11.12.11 ADC regular sequence register 3 (ADC_SQR3) Address offset: 0x34 Reset value: 0x0000 0000 SQ6[4:0] SQ5[4:0] SQ4[4:1] Reserved SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0] Bits 31:30 Reserved, must be kept at reset value. Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence These bits are written by software with the channel number (0..17) assigned as the 6th in the sequence to be converted.
Page 249: Adc Injected Sequence Register (Adc_Jsqr)
Analog-to-digital converter (ADC) RM0008 11.12.12 ADC injected sequence register (ADC_JSQR) Address offset: 0x38 Reset value: 0x0000 0000 JL[1:0] JSQ4[4:1] Reserved JSQ4_0 JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] Bits 31:22 Reserved, must be kept at reset value. Bits 21:20 JL[1:0]: Injected sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence.
Page 250: Adc Injected Data Register X (Adc_Jdrx) (X= 1
RM0008 Analog-to-digital converter (ADC) 11.12.13 ADC injected data register x (ADC_JDRx) (x= 1..4) Address offset: 0x3C - 0x48 Reset value: 0x0000 0000 Reserved JDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read only. They contain the conversion result from injected channel x. The data is left or right-aligned as shown in Figure 27 Figure...
Page 251: 11.12.15 Adc Register Map
Analog-to-digital converter (ADC) RM0008 11.12.15 ADC register map The following table summarizes the ADC registers. Table 72. ADC register map and reset values Offset Register ADC_SR 0x00 Reserved Reset value DISC DUALMOD ADC_CR1 AWDCH[4:0] 0x04 Reserved [3:0] [2:0] Reset value JEXTSE EXTSEL ADC_CR2...
Page 252 RM0008 Analog-to-digital converter (ADC) Table 72. ADC register map and reset values (continued) Offset Register SQ16[4:0] 16th SQ15[4:0] 15th SQ14[4:0] 14th SQ13[4:0] 13th conversion in conversion in conversion in conversion in ADC_SQR1 L[3:0] regular regular regular regular 0x2C Reserved sequence bits sequence bits sequence bits sequence bits...
Page 253: Digital-To-Analog Converter (Dac)
Digital-to-analog converter (DAC) RM0008 Digital-to-analog converter (DAC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 254: Table 73. Dac Pins
RM0008 Digital-to-analog converter (DAC) Figure 40. DAC channel block diagram DAC control register TSELx[2:0] bits SWTR IGx TIM2_T RGO DMAENx TIM4_T RGO TIM5_T RGO TIM6_T RGO TIM7_T RGO TIM8_T RGO EXTI_9 DM A req ue stx Control logicx TENx 12-bit DHRx MAMPx[3:0] bits trianglex...
Page 255: Dac Functional Description
Digital-to-analog converter (DAC) RM0008 12.3 DAC functional description 12.3.1 DAC channel enable Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time t WAKEUP Note: The ENx bit enables the analog DAC Channelx macrocell only.
Page 256: Dac Conversion
RM0008 Digital-to-analog converter (DAC) Figure 41. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into DAC_DHR8RD [7:0] bits (stored into DHR1[11:4] bits) and data for DAC channel2 to be loaded into DAC_DHR8RD [15:8] bits (stored into DHR2[11:4] bits) –...
Page 257: Dac Output Voltage
Digital-to-analog converter (DAC) RM0008 Figure 43. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 12.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation:...
Page 258: Dma Request
RM0008 Digital-to-analog converter (DAC) Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, it takes only one APB1 clock cycle for DAC_DHRx-to- DAC_DORx register transfer. 12.3.7 DMA request Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.
Page 259: Triangle-Wave Generation
Digital-to-analog converter (DAC) RM0008 Figure 45. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK 0x00 0xD55 0xAAA SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. 12.3.9 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
Page 260: Dual Dac Channel Conversion
RM0008 Digital-to-analog converter (DAC) Figure 47. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: DAC trigger must be enabled for noise generation, by setting the TENx bit in the DAC_CR register. MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
Page 261: Independent Trigger With Same Lfsr Generation
Digital-to-analog converter (DAC) RM0008 12.4.2 Independent trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 262: Independent Trigger With Different Triangle Generation
RM0008 Digital-to-analog converter (DAC) DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then updated. When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same triangle amplitude, is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later).
Page 263: Simultaneous Trigger With Same Lfsr Generation
Digital-to-analog converter (DAC) RM0008 12.4.8 Simultaneous trigger with same LFSR generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 264: Simultaneous Trigger With Different Triangle Generation
RM0008 Digital-to-analog converter (DAC) added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then updated. 12.4.11 Simultaneous trigger with different triangle generation To configure the DAC in this conversion mode, the following sequence is required: •...
Page 265 Digital-to-analog converter (DAC) RM0008 Bits 31:29 Reserved. Bit 28 DMAEN2: DAC channel2 DMA enable This bit is set and cleared by software. 0: DAC channel2 DMA mode disabled 1: DAC channel2 DMA mode enabled Bit 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.
Page 266 RM0008 Digital-to-analog converter (DAC) Bit 17 BOFF2: DAC channel2 output buffer disable This bit set and cleared by software to enable/disable DAC channel2 output buffer. 0: DAC channel2 output buffer enabled 1: DAC channel2 output buffer disabled Bit 16 EN2: DAC channel2 enable This bit set and cleared by software to enable/disable DAC channel2.
Page 267: Dac Software Trigger Register (Dac_Swtrigr)
Digital-to-analog converter (DAC) RM0008 Bit 2 TEN1: DAC channel1 trigger enable This bit set and cleared by software to enable/disable DAC channel1 trigger 0: DAC channel1 trigger disabled and data written into DAC_DHRx register is transferred one APB1 clock cycle later to the DAC_DOR1 register. 1: DAC channel1 trigger enabled and data transfer from DAC_DHRx register is transferred three APB1 clock cycles later to the DAC_DOR1 register.
Page 268: Dac Channel1 12-Bit Right-Aligned Data Holding Register
RM0008 Digital-to-analog converter (DAC) 12.5.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) Address offset: 0x08 Reset value: 0x0000 0000 Reserved DACC1DHR[11:0] Reserved Bits 31:12 Reserved. Bit 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel1. 12.5.4 DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
Page 269: Dac Channel2 12-Bit Right Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0008 12.5.6 DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) Address offset: 0x14 Reset value: 0x0000 0000 Reserved DACC2DHR[11:0] Reserved Bits 31:12 Reserved. Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. 12.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
Page 270: Dual Dac 12-Bit Right-Aligned Data Holding Register (Dac_Dhr12Rd)
RM0008 Digital-to-analog converter (DAC) 12.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) Address offset: 0x20 Reset value: 0x0000 0000 DACC2DHR[11:0] Reserved DACC1DHR[11:0] Reserved Bits 31:28 Reserved. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specify 12-bit data for DAC channel2. Bits 15:12 Reserved.
Page 271: Dual Dac 8-Bit Right Aligned Data Holding Register
Digital-to-analog converter (DAC) RM0008 12.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Reserved DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel2. Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data These bits are written by software which specify 8-bit data for DAC channel1.
Page 272: Dac Register Map
RM0008 Digital-to-analog converter (DAC) 12.5.14 DAC register map The following table summarizes the DAC registers. Table 75. DAC register map Offset Register TSEL2[2: TSEL1 DAC_CR MAMP2[3:0] E2[2: MAMP1[3:0] E1[2: 0x00 [2:0] Res. Res. Reset value DAC_SWTRIGR 0x04 Reserved Reset value DAC_DHR12R1 DACC1DHR[11:0] 0x08...
Page 273: Direct Memory Access Controller (Dma)
Direct memory access controller (DMA) RM0008 Direct memory access controller (DMA) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 274: Figure 48. Dma Block Diagram In Connectivity Line Devices
RM0008 Direct memory access controller (DMA) Figure 48. DMA block diagram in connectivity line devices DocID13902 Rev 15 274/1128...
Page 275: Dma Functional Description
Direct memory access controller (DMA) RM0008 Figure 49. DMA block diagram in low-, medium- high- and XL-density devices ICode Flash FLITF DCode Cortex-M3 Sys tem SRAM DMA1 Ch.1 FSMC Ch.2 SDIO Bridge 2 AHB System Ch.7 APB2 Bridge 1 APB1 Arbiter USART1 TIM2...
Page 276: Arbiter
RM0008 Direct memory access controller (DMA) In summary, each DMA transfer consists of three operations: • The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register •...
Page 277 Direct memory access controller (DMA) RM0008 transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in noncircular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled.
Page 278: Programmable Data Width, Data Alignment And Endians
RM0008 Direct memory access controller (DMA) register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. 13.3.4 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 76: Programmable data width &...
Page 279: Error Management
Direct memory access controller (DMA) RM0008 Table 76. Programmable data width & endian behavior (when bits PINC = MINC = 1) (continued) Number Desti- Source of data nation Source content: Destination content: port items to Transfer operations port address / data address / data width transfer...
Page 280: Interrupts
RM0008 Direct memory access controller (DMA) 13.3.6 Interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 77. DMA interrupt requests Interrupt event Event flag Enable Control bit Half-transfer...
Page 281 Direct memory access controller (DMA) RM0008 Figure 50. DMA1 request mapping Fixed hardware priority Peripheral request signals High priority ADC1 HW request 1 Channel 1 TIM2_CH3 TIM4_CH1 SW trigger (MEM2MEM bit) Channel 1 EN bit USART3_TX TIM1_CH1 HW request 2 Channel 2 TIM2_UP TIM3_CH3...
Page 282: Table 78. Summary Of Dma1 Requests For Each Channel
RM0008 Direct memory access controller (DMA) Table 78 lists the DMA requests for each channel. Table 78. Summary of DMA1 requests for each channel Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 ADC1 ADC1 SPI/I SPI1_RX...
Page 283: Table 79. Summary Of Dma2 Requests For Each Channel
Direct memory access controller (DMA) RM0008 Figure 51. DMA2 request mapping Peripheral request signals Fixed hardware priority TIM5_CH4 HIGH PRIORITY TIM5_TRIG HW request 1 Channel 1 TIM8_CH3 TIM8_UP SW trigger (MEM2MEM bit) SPI/I2S3_RX Channel 1 EN bit TIM8_CH4 HW request 2 TIM8_TRIG Channel 2 TIM8_COM...
Page 284: Dma Registers
RM0008 Direct memory access controller (DMA) 1. ADC3, SDIO and TIM8 DMA requests are available only in high-density and XL-density devices. 13.4 DMA registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. Note: In the following registers, all bits related to channel6 and channel7 are not relevant for DMA2 since it has only 5 channels.
Page 285: Dma Interrupt Flag Clear Register (Dma
Direct memory access controller (DMA) RM0008 13.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF CHTIF CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 Reserved CTEIF CHTIF CTCIF CTEIF CHTIF CGIF4 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 Bits 31:28 Reserved, must be kept at reset value.
Page 286: Dma Channel X Configuration Register (Dma_Ccrx) (X = 1
RM0008 Direct memory access controller (DMA) 13.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7, where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Reserved MEM2 PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC...
Page 287: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
Direct memory access controller (DMA) RM0008 Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable...
Page 288: Dma Channel X Peripheral Address Register (Dma_Cparx) (X = 1
RM0008 Direct memory access controller (DMA) 13.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7), where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 PA[31:0]: Peripheral address...
Page 289: Dma Register Map
Direct memory access controller (DMA) RM0008 13.4.7 DMA register map The following table gives the DMA register map and the reset values. Table 80. DMA register map and reset values Offset Register DMA_ISR 0x000 Reserved Reset value DMA_IFCR 0x004 Reserved Reset value DMA_CCR1 [1:0]...
Page 290 RM0008 Direct memory access controller (DMA) Table 80. DMA register map and reset values (continued) Offset Register DMA_CMAR3 MA[31:0] 0x03C Reset value 0x040 Reserved DMA_CCR4 [1:0] 0x044 Reserved Reset value DMA_CNDTR4 NDT[15:0] 0x048 Reserved Reset value DMA_CPAR4 PA[31:0] 0x04C Reset value DMA_CMAR4 MA[31:0] 0x050...
Page 291 Direct memory access controller (DMA) RM0008 Table 80. DMA register map and reset values (continued) Offset Register DMA_CNDTR7 NDT[15:0] 0x084 Reserved Reset value DMA_CPAR7 PA[31:0] 0x088 Reset value DMA_CMAR7 MA[31:0] 0x08C Reset value 0x090 Reserved Refer to Table 3 on page 51 for the register boundary addresses.
Page 292: Advanced-Control Timers (Tim1&Tim8)
RM0008 Advanced-control timers (TIM1&TIM8) Advanced-control timers (TIM1&TIM8) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 293: Tim1&Tim8 Main Features
Advanced-control timers (TIM1&TIM8) RM0008 14.2 TIM1&TIM8 main features TIM1&TIM8 timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock frequency either by any factor between 1 and 65536. •...
Page 294: Figure 52. Advanced-Control Timer Block Diagram
RM0008 Advanced-control timers (TIM1&TIM8) Figure 52. Advanced-control timer block diagram Internal Clock (CK_INT) CK_TIM18 from RCC ETRF Trigger ETRP Controller Polarity Selection & Edge TRGO TIMx_ETR Input Filter Detector & Prescaler to other timers ITR0 to DAC/ADC ITR1 Slave Reset, Enable, Up/Down, Count ITR2 Mode TRGI...
Page 295: Tim1&Tim8 Functional Description
Advanced-control timers (TIM1&TIM8) RM0008 14.3 TIM1&TIM8 functional description 14.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 296: Counter Modes
RM0008 Advanced-control timers (TIM1&TIM8) Figure 53. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 54.
Page 297: Figure 55. Counter Timing Diagram, Internal Clock Divided By 1
Advanced-control timers (TIM1&TIM8) RM0008 preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent).
Page 298: Figure 57. Counter Timing Diagram, Internal Clock Divided By 4
RM0008 Advanced-control timers (TIM1&TIM8) Figure 57. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 58. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 299: Figure 60. Counter Timing Diagram, Update Event When Arpe=1
Advanced-control timers (TIM1&TIM8) RM0008 Figure 60. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register Write a new value in TIMx_ARR...
Page 300: Figure 61. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 Advanced-control timers (TIM1&TIM8) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 61. Counter timing diagram, internal clock divided by 1 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV)
Page 301: Figure 64. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timers (TIM1&TIM8) RM0008 Figure 64. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 65. Counter timing diagram, update event when repetition counter is not used CK_PSC Timer clock = CK_CNT...
Page 302: Figure 66. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
RM0008 Advanced-control timers (TIM1&TIM8) The UEV update event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 303: Figure 67. Counter Timing Diagram, Internal Clock Divided By 2
Advanced-control timers (TIM1&TIM8) RM0008 Figure 67. Counter timing diagram, internal clock divided by 2 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 68. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 CK_PSC CNT_EN Timer clock = CK_CNT...
Page 304: Repetition Counter
RM0008 Advanced-control timers (TIM1&TIM8) Figure 70. Counter timing diagram, update event with ARPE=1 (counter underflow) CK_PSC Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR Auto-reload active register...
Page 305: Figure 72. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1&TIM8) RM0008 The repetition counter is decremented: • At each counter overflow in upcounting mode, • At each counter underflow in downcounting mode, • At each counter overflow and at each counter underflow in center-aligned mode. Although this limits the maximum number of repetition to 128 PWM cycles, it makes it possible to update the duty cycle twice per PWM period.
Page 306: Clock Selection
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for example, you can configure Timer 1 to act as a prescaler for Timer 2.
Page 307: Figure 75. Control Circuit In External Clock Mode 1
Advanced-control timers (TIM1&TIM8) RM0008 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 308: Capture/Compare Channels
RM0008 Advanced-control timers (TIM1&TIM8) For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 309: Figure 78. Capture/Compare Channel (Example: Channel 1 Input Stage)
Advanced-control timers (TIM1&TIM8) RM0008 Figure 78. Capture/compare channel (example: channel 1 input stage) TI1F_ED to the slave mode controller TI1F_Rising TI1F TI1FP1 filter Edge downcounter Detector TI1F_Falling TI2FP1 IC1PS divider /1, /2, /4, /8 ICF[3:0] CC1P/CC1NP TIMx_CCER (from slave mode TIMx_CCMR1 controller) TI2F_rising...
Page 310: Input Capture Mode
RM0008 Advanced-control timers (TIM1&TIM8) Figure 80. Output stage of capture/compare channel (channel 1 to 3) To the master mode controller Output enable ‘0’ circuit OC1_DT CC1P CNT>CCR1 OC1REF Output mode Dead-time TIM1_CCER CNT=CCR1 controller generator OC1N_DT OC1N Output ‘0’ enable circuit CC1NE CC1E TIM1_CCER...
Page 311: Pwm Input Mode
Advanced-control timers (TIM1&TIM8) RM0008 The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: • Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register.
Page 312: Forced Output Mode
RM0008 Advanced-control timers (TIM1&TIM8) For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): • Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected).
Page 313: Output Compare Mode
Advanced-control timers (TIM1&TIM8) RM0008 Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the output compare mode section below. 14.3.9 Output compare mode This function is used to control an output waveform or indicating when a period of time has...
Page 314: Pwm Mode
RM0008 Advanced-control timers (TIM1&TIM8) Figure 83. Output compare mode, toggle on OC1. Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 14.3.10 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 315: Figure 84. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1&TIM8) RM0008 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 296. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 316: Figure 85. Center-Aligned Pwm Waveforms (Arr=8)
RM0008 Advanced-control timers (TIM1&TIM8) Figure 85. Center-aligned PWM waveforms (ARR=8) Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Page 317: Complementary Outputs And Dead-Time Insertion
Advanced-control timers (TIM1&TIM8) RM0008 14.3.11 Complementary outputs and dead-time insertion The advanced-control timers (TIM1&TIM8) can output two complementary signals and manage the switching-off and the switching-on instants of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 318: Using The Break Function
RM0008 Advanced-control timers (TIM1&TIM8) Figure 88. Dead-time waveforms with delay greater than the positive pulse. OCxREF OCxN delay The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 14.4.18: TIM1&TIM8 break and dead- time register (TIMx_BDTR) on page 354 for delay calculation.
Page 319 Advanced-control timers (TIM1&TIM8) RM0008 must insert a delay (dummy instruction) before reading it correctly. This is because you write the asynchronous signal and read the synchronous signal. When a break occurs (selected level on the break input): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or in reset state (selected by the OSSI bit).
Page 320: Figure 89. Output Behavior In Response To A Break
RM0008 Advanced-control timers (TIM1&TIM8) Figure 89. Output behavior in response to a break. BREAK (MOE OCxREF (OCxN not implemented, CCxP=0, OISx=1) (OCxN not implemented, CCxP=0, OISx=0) (OCxN not implemented, CCxP=1, OISx=1) (OCxN not implemented, CCxP=1, OISx=0) delay delay delay OCxN (CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1) delay delay...
Page 321: Clearing The Ocxref Signal On An External Event
Advanced-control timers (TIM1&TIM8) RM0008 14.3.13 Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs.
Page 322: 6-Step Pwm Generation
RM0008 Advanced-control timers (TIM1&TIM8) 14.3.14 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 323: One-Pulse Mode
Advanced-control timers (TIM1&TIM8) RM0008 14.3.15 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 324: Encoder Interface Mode
RM0008 Advanced-control timers (TIM1&TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 325: Table 81. Counting Direction Versus Encoder Signals
Advanced-control timers (TIM1&TIM8) RM0008 repetition counter, trigger output features continue to work as normal. Encoder mode and External clock mode 2 are not compatible and must not be selected together. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position.
Page 326: Timer Input Xor Function
RM0008 Advanced-control timers (TIM1&TIM8) Figure 93. Example of counter operation in encoder interface mode. forward jitter backward jitter forward Counter down Figure 94 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 94.
Page 327: Interfacing With Hall Sensors
Advanced-control timers (TIM1&TIM8) RM0008 14.3.17 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and TIMx_CH3.
Page 328: Figure 95. Example Of Hall Sensor Interface
RM0008 Advanced-control timers (TIM1&TIM8) written after a COM event for the next step (this can be done in an interrupt subroutine generated by the rising edge of OC2REF). Figure 95 describes this example. Figure 95. Example of hall sensor interface TIH1 TIH2 TIH3...
Page 329: Timx And External Trigger Synchronization
Advanced-control timers (TIM1&TIM8) RM0008 14.3.19 TIMx and external trigger synchronization The TIMx timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 330: Figure 97. Control Circuit In Gated Mode
RM0008 Advanced-control timers (TIM1&TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 331: Figure 98. Control Circuit In Trigger Mode
Advanced-control timers (TIM1&TIM8) RM0008 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: • Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 332: Timer Synchronization
RM0008 Advanced-control timers (TIM1&TIM8) Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01 in TIMx_CCMR1 register to select only the input capture source –...
Page 333: Tim1&Tim8 Registers
Advanced-control timers (TIM1&TIM8) RM0008 14.4 TIM1&TIM8 registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 14.4.1 TIM1&TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0]...
Page 334: Tim1&Tim8 Control Register 2 (Timx_Cr2)
RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 335 Advanced-control timers (TIM1&TIM8) RM0008 Bit 10 OIS2: Output Idle state 2 (OC2 output) refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 336 RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 337: Tim1&Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.3 TIM1&TIM8 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] Res. SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge.
Page 338 RM0008 Advanced-control timers (TIM1&TIM8) Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 339: Tim1&Tim8 Dma/Interrupt Enable Register (Timx_Dier)
Advanced-control timers (TIM1&TIM8) RM0008 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 340 RM0008 Advanced-control timers (TIM1&TIM8) Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled 1: CC4 DMA request enabled Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled 1: CC3 DMA request enabled Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled...
Page 341: Tim1&Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.5 TIM1&TIM8 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC4OF CC3OF CC2OF CC1OF Res. COMIF CC4IF CC3IF CC2IF CC1IF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Res. rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:13 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag...
Page 342: Tim1&Tim8 Event Generation Register (Timx_Egr)
RM0008 Advanced-control timers (TIM1&TIM8) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/Compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 343 Advanced-control timers (TIM1&TIM8) RM0008 Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.
Page 344: Tim1&Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.7 TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 345 Advanced-control timers (TIM1&TIM8) RM0008 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 346 RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 347: Tim1&Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.8 TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M[2:0] OC3M[2:0] CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable...
Page 348: Tim1&Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0008 Advanced-control timers (TIM1&TIM8) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 349 Advanced-control timers (TIM1&TIM8) RM0008 Bit 7 CC2NP: Capture/Compare 2 complementary output polarity refer to CC1NP description Bit 6 CC2NE: Capture/Compare 2 complementary output enable refer to CC1NE description Bit 5 CC2P: Capture/Compare 2 output polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity 0: OC1N active high.
Page 350: Table 83. Output Control Bits For Complementary Ocx And Ocxn Channels With
RM0008 Advanced-control timers (TIM1&TIM8) Table 83. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states OSSI OSSR CCxE CCxNE OCx output state OCxN output state Output Disabled (not driven by Output Disabled (not driven by the the timer) timer) OCx=0, OCx_EN=0...
Page 351: Tim1&Tim8 Counter (Timx_Cnt)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.10 TIM1&TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 14.4.11 TIM1&TIM8 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency (CK_CNT) is equal to f / (PSC[15:0] + 1).
Page 352: Tim1&Tim8 Repetition Counter Register (Timx_Rcr)
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.13 TIM1&TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 353: Tim1&Tim8 Capture/Compare Register 2 (Timx_Ccr2)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.15 TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 354: Tim1&Tim8 Capture/Compare Register 4 (Timx_Ccr4)
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.17 TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 355 Advanced-control timers (TIM1&TIM8) RM0008 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 356: Tim1&Tim8 Dma Control Register (Timx_Dcr)
RM0008 Advanced-control timers (TIM1&TIM8) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 357: Tim1&Tim8 Dma Address For Full Transfer (Timx_Dmar)
Advanced-control timers (TIM1&TIM8) RM0008 14.4.20 TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the...
Page 358: Tim1&Tim8 Register Map
RM0008 Advanced-control timers (TIM1&TIM8) 14.4.21 TIM1&TIM8 register map TIM1&TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 84. TIM1&TIM8 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved...
Page 359 Advanced-control timers (TIM1&TIM8) RM0008 Table 84. TIM1&TIM8 register map and reset values (continued) Offset Register TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reserved Reset value TIMx_CCR4 CCR4[15:0] 0x40 Reserved Reset value LOCK TIMx_BDTR DT[7:0] [1:0]...
Page 360: General-Purpose Timers (Tim2 To Tim5)
RM0008 General-purpose timers (TIM2 to TIM5) General-purpose timers (TIM2 to TIM5) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 361: Timx Main Features
General-purpose timers (TIM2 to TIM5) RM0008 15.2 TIMx main features General-purpose TIMx timer features include: • 16-bit up, down, up/down auto-reload counter. • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536. •...
Page 362: Timx Functional Description
RM0008 General-purpose timers (TIM2 to TIM5) Figure 100. General-purpose timer block diagram Internal Clock (CK_INT) TIMxCLK from RCC ETRF ETRP Polarity selection & edge TIMx_ETR Input filter detector & prescaler TRGO ITR0 Trigger to other timers ITR1 controller to DAC/ADC ITR2 TRGI Slave...
Page 363: Figure 101. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2 to TIM5) RM0008 The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register.
Page 364: Counter Modes
RM0008 General-purpose timers (TIM2 to TIM5) Figure 102. Counter timing diagram with prescaler division change from 1 to 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter 15.3.2...
Page 365: Figure 103. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0008 Figure 103. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 104.
Page 366: Figure 106. Counter Timing Diagram, Internal Clock Divided By N
RM0008 General-purpose timers (TIM2 to TIM5) Figure 106. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 107. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) CK_INT CNT_EN...
Page 367: Figure 108. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2 to TIM5) RM0008 Figure 108. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC CNT_EN Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 368: Figure 109. Counter Timing Diagram, Internal Clock Divided By 1
RM0008 General-purpose timers (TIM2 to TIM5) Figure 109. Counter timing diagram, internal clock divided by 1 CK_INT CNT_EN Timer clock = CK_CNT Counter register 04 03 02 01 00 35 34 33 32 31 30 2F Counter underflow (cnt_udf) Update event (UEV) Update interrupt flag (UIF) Figure 110.
Page 369: Figure 112. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2 to TIM5) RM0008 Figure 112. Counter timing diagram, internal clock divided by N CK_INT Timer clock = CK_CNT Counter register Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 113. Counter timing diagram, Update event CK_INT CNT_EN Timer clock = CK_CNT Counter register...
Page 370: Figure 114. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
RM0008 General-purpose timers (TIM2 to TIM5) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value.
Page 371: Figure 115. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2 to TIM5) RM0008 Figure 115. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN TImer clock = CK_CNT Counter register 0003 0002 0001 0000 0001 0002 0003 Counter underflow Update event (UEV) Update interrupt flag (UIF) Figure 116.
Page 372: Clock Selection
RM0008 General-purpose timers (TIM2 to TIM5) Figure 118. Counter timing diagram, Update event with ARPE=1 (counter underflow) CK_INT CNT_EN Timer clock = CK_CNT Counter register 05 04 03 02 01 01 02 03 04 05 06 07 Counter underflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Write a new value in TIMx_ARR...
Page 373: Figure 120. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM2 to TIM5) RM0008 Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically).
Page 374: Figure 122. Control Circuit In External Clock Mode 1
RM0008 General-purpose timers (TIM2 to TIM5) Note: The capture prescaler is not used for triggering, so you don’t need to configure it. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register.
Page 375: Capture/Compare Channels
General-purpose timers (TIM2 to TIM5) RM0008 As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 376: Figure 126. Capture/Compare Channel 1 Main Circuit
RM0008 General-purpose timers (TIM2 to TIM5) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 126. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress...
Page 377: Input Capture Mode
General-purpose timers (TIM2 to TIM5) RM0008 15.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 378: Pwm Input Mode
RM0008 General-purpose timers (TIM2 to TIM5) 15.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 379: Forced Output Mode
General-purpose timers (TIM2 to TIM5) RM0008 15.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter.
Page 380: Pwm Mode
RM0008 General-purpose timers (TIM2 to TIM5) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 129.
Page 381: Figure 130. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2 to TIM5) RM0008 This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low.
Page 382: Figure 131. Center-Aligned Pwm Waveforms (Arr=8)
RM0008 General-purpose timers (TIM2 to TIM5) Figure 131 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 383: One-Pulse Mode
General-purpose timers (TIM2 to TIM5) RM0008 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 384: Clearing The Ocxref Signal On An External Event
RM0008 General-purpose timers (TIM2 to TIM5) Let’s use TI2FP2 as trigger 1: • Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. • TI2FP2 must detect a rising edge, write CC2P=0 in the TIMx_CCER register. • Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register.
Page 385: Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0008 The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. The external clock mode 2 must be disabled: bit ECE in the TIM1_SMCR register is cleared to 0. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs.
Page 386: Table 85. Counting Direction Versus Encoder Signals
RM0008 General-purpose timers (TIM2 to TIM5) In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time.
Page 387: Figure 134. Example Of Counter Operation In Encoder Interface Mode
General-purpose timers (TIM2 to TIM5) RM0008 Figure 134. Example of counter operation in encoder interface mode forward jitter backward jitter forward Counter down Figure 135 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 135.
Page 388: Timer Input Xor Function
RM0008 General-purpose timers (TIM2 to TIM5) 15.3.13 Timer input XOR function The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 389: Figure 137. Control Circuit In Gated Mode
General-purpose timers (TIM2 to TIM5) RM0008 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 390: Figure 138. Control Circuit In Trigger Mode
RM0008 General-purpose timers (TIM2 to TIM5) Figure 138. Control circuit in trigger mode CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 35 36 37 38 Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode).
Page 391: Timer Synchronization
General-purpose timers (TIM2 to TIM5) RM0008 Figure 139. Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock = CK_CNT = CK_PSC Counter register 15.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode.
Page 392: Figure 141. Gating Timer 2 With Oc1Ref Of Timer 1
RM0008 General-purpose timers (TIM2 to TIM5) Using one timer to enable another timer In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1. Refer to Figure 140 for connections. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high.
Page 393: Figure 142. Gating Timer 2 With Enable Of Timer 1
General-purpose timers (TIM2 to TIM5) RM0008 timers. Timer 2 stops when Timer 1 is disabled by writing ‘0 to the CEN bit in the TIM1_CR1 register: • Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIM1_CR2 register).
Page 394: Figure 143. Triggering Timer 2 With Update Of Timer 1
RM0008 General-purpose timers (TIM2 to TIM5) Figure 143. Triggering timer 2 with update of timer 1 CK_INT TIMER1-UEV TIMER1-CNT TIMER2-CNT TIMER2-CEN=CNT_EN TIMER 2-TIF Write TIF=0 As in the previous example, you can initialize both counters before starting counting. Figure 144 shows the behavior with the same configuration as in Figure 141 but in trigger...
Page 395 General-purpose timers (TIM2 to TIM5) RM0008 Using one timer as prescaler for another timer For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Figure 140 for connections. To do this: • Configure Timer 1 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM1_CR2 register).
Page 396: Debug Mode
RM0008 General-purpose timers (TIM2 to TIM5) Figure 145. Triggering timer 1 and 2 with timer 1 TI1 input CK_INT TIMER 1-TI1 TIMER1-CEN=CNT_EN TIMER 1-CK_PSC TIMER1-CNT 02 03 04 05 06 07 08 09 TIMER1-TIF TIMER2-CEN=CNT_EN TIMER 2-CK_PSC TIMER2-CNT 02 03 04 05 06 07 08 09 TIMER2-TIF 15.3.16 Debug mode...
Page 397: Timx2 To Tim5 Registers
General-purpose timers (TIM2 to TIM5) RM0008 15.4 TIMx2 to TIM5 registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits).
Page 398 RM0008 General-purpose timers (TIM2 to TIM5) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: –...
Page 399: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 TI1S MMS[2:0] CCDS Reserved Reserved Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) See also Section 14.3.18: Interfacing with Hall sensors on page 327...
Page 400: Timx Slave Mode Control Register (Timx_Smcr)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 ETPS[1:0] ETF[3:0] TS[2:0] SMS[2:0] Res. Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable...
Page 401: Table 86. Timx Internal Trigger Connection
General-purpose timers (TIM2 to TIM5) RM0008 Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Internal Trigger 3 (ITR3). 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 402: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 CC4DE CC3DE CC2DE CC1DE CC4IE CC3IE CC2IE CC1IE Res. Res. Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 403: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2 to TIM5) RM0008 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 404 RM0008 General-purpose timers (TIM2 to TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description).
Page 405: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 CC4G CC3G CC2G CC1G Reserved Res. Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 406: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 407 General-purpose timers (TIM2 to TIM5) RM0008 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 408 RM0008 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output.
Page 409: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE CC4S[1:0] CC3S[1:0] IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0] Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode...
Page 410: Timx Capture/Compare Enable Register (Timx_Ccer)
RM0008 General-purpose timers (TIM2 to TIM5) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 411: Timx Counter (Timx_Cnt)
General-purpose timers (TIM2 to TIM5) RM0008 Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bits 3:2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low.
Page 412: Timx Prescaler (Timx_Psc)
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded in the active prescaler register at each update event. 15.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 413: Timx Capture/Compare Register 2 (Timx_Ccr2)
General-purpose timers (TIM2 to TIM5) RM0008 15.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 414: Timx Dma Control Register (Timx_Dcr)
RM0008 General-purpose timers (TIM2 to TIM5) Bits 15:0 CCR4[15:0]: Capture/Compare value if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE).
Page 415 General-purpose timers (TIM2 to TIM5) RM0008 Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 416: Timx Register Map
RM0008 General-purpose timers (TIM2 to TIM5) 15.4.19 TIMx register map TIMx registers are mapped as described in the table below: Table 88. TIMx register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reserved Reset value TIMx_CR2 [2:0] 0x04 Reserved Reset value ETPS...
Page 417 General-purpose timers (TIM2 to TIM5) RM0008 Table 88. TIMx register map and reset values (continued) Offset Register TIMx_ARR ARR[15:0] 0x2C Reserved Reset value 0x30 Reserved TIMx_CCR1 CCR1[15:0] 0x34 Reserved Reset value TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value TIMx_CCR3 CCR3[15:0] 0x3C Reserved Reset value TIMx_CCR4...
Page 418: General-Purpose Timers (Tim9 To Tim14)
RM0008 General-purpose timers (TIM9 to TIM14) General-purpose timers (TIM9 to TIM14) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 419: Tim9 To Tim14 Main Features
General-purpose timers (TIM9 to TIM14) RM0008 16.2 TIM9 to TIM14 main features 16.2.1 TIM9/TIM12 main features The features of the TIM9 to TIM14 general-purpose timers include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”) •...
Page 420: Tim10/Tim11 And Tim13/Tim14 Main Features
RM0008 General-purpose timers (TIM9 to TIM14) 16.2.2 TIM10/TIM11 and TIM13/TIM14 main features The features of general-purpose timers TIM10/TIM11 and TIM13/TIM14 include: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65536 (can be changed “on the fly”) •...
Page 421: Tim9 To Tim14 Functional Description
General-purpose timers (TIM9 to TIM14) RM0008 16.3 TIM9 to TIM14 functional description 16.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 422: Counter Modes
RM0008 General-purpose timers (TIM9 to TIM14) Figure 148. Counter timing diagram with prescaler division change from 1 to 2 CK_PSC Timer clock = CK_CNT Counter register F9 FA FB FC Update event (UEV) Prescaler control register Write a new value in TIMx_PSC Prescaler buffer Prescaler counter Figure 149.
Page 423: Figure 150. Counter Timing Diagram, Internal Clock Divided By 1
General-purpose timers (TIM9 to TIM14) RM0008 setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 424: Figure 152. Counter Timing Diagram, Internal Clock Divided By 4
RM0008 General-purpose timers (TIM9 to TIM14) Figure 152. Counter timing diagram, internal clock divided by 4 CK_PSC CNT_EN Timer clock = CK_CNT Counter register 0035 0036 0000 0001 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 153. Counter timing diagram, internal clock divided by N CK_PSC Timer clock = CK_CNT Counter register...
Page 425: Clock Selection
General-purpose timers (TIM9 to TIM14) RM0008 Figure 155. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) CK_PSC Timer clock = CK_CNT Counter register F1 F2 F3 F4 F5 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload preload register Auto-reload shadow register...
Page 426: Figure 156. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0008 General-purpose timers (TIM9 to TIM14) Figure 156. Control circuit in normal mode, internal clock divided by 1 Internal clock CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 External clock source mode 1( TIM9 and TIM1 This mode is selected when SMS=’111’...
Page 427: Capture/Compare Channels
General-purpose timers (TIM9 to TIM14) RM0008 Figure 158. Control circuit in external clock mode 1 CNT_EN Counter clock = CK_CNT = CK_PSC Counter register Write TIF=0 16.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 428: Input Capture Mode
RM0008 General-purpose timers (TIM9 to TIM14) Figure 160. Capture/compare channel 1 main circuit APB Bus MCU-peripheral interface write CCR1H write_in_progress read CCR1H read_in_progress write CCR1L Capture/compare preload register read CCR1L CC1S[1] output compare_transfer capture_transfer mode CC1S[0] input CC1S[1] OC1PE mode OC1PE Capture/compare shadow register CC1S[0]...
Page 429: Pwm Input Mode (Only For Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0008 cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises.
Page 430: Forced Output Mode
RM0008 General-purpose timers (TIM9 to TIM14) Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’...
Page 431: Output Compare Mode
General-purpose timers (TIM9 to TIM14) RM0008 16.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP...
Page 432: Pwm Mode
RM0008 General-purpose timers (TIM9 to TIM14) Figure 163. Output compare mode, toggle on OC1. Write B201h in the CC1R register B200 B201 TIM1_CNT 0039 003A 003B TIM1_CCR1 003A B201 oc1ref=OC1 Match detected on CCR1 Interrupt generated if enabled 16.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 433: One-Pulse Mode
General-purpose timers (TIM9 to TIM14) RM0008 Figure 164. Edge-aligned PWM waveforms (ARR=8) Counter register OCXREF CCRx=4 CCxIF OCXREF CCRx=8 CCxIF OCXREF CCRx>8 CCxIF OCXREF CCRx=0 CCxIF 16.3.10 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
Page 434: Tim9/12 External Trigger Synchronization
RM0008 General-purpose timers (TIM9 to TIM14) For example you may want to generate a positive pulse on OC1 with a length of t PULSE after a delay of t as soon as a positive edge is detected on the TI2 input pin. DELAY Use TI2FP2 as trigger 1: Map TI2FP2 to TI2 by writing CC2S=’01’...
Page 435: Figure 166. Control Circuit In Reset Mode
General-purpose timers (TIM9 to TIM14) RM0008 Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 436: Figure 167. Control Circuit In Gated Mode
RM0008 General-purpose timers (TIM9 to TIM14) The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops.
Page 437: Timer Synchronization (Tim9/12)
General-purpose timers (TIM9 to TIM14) RM0008 16.3.12 Timer synchronization (TIM9/12) The TIM timers are linked together internally for timer synchronization or chaining. Refer to Section 15.3.15: Timer synchronization on page 391 for details. 16.3.13 Debug mode ® When the microcontroller enters debug mode (Cortex -M3 core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module.
Page 438 RM0008 General-purpose timers (TIM9 to TIM14) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow –...
Page 439: 9/12Tim9/12 Slave Mode Control Register (Timx_Smcr)
General-purpose timers (TIM9 to TIM14) RM0008 16.4.2 9/12TIM9/12 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 TS[2:0] SMS[2:0] Reserved Res. Bits 6:4 TS: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Internal Trigger 2 (ITR2)
Page 440: Tim9/12 Interrupt Enable Register (Timx_Dier)
RM0008 General-purpose timers (TIM9 to TIM14) Table 89. TIMx internal trigger connection Slave TIM ITR0 (TS =’ 000’) ITR1 (TS = ‘001’) ITR2 (TS = ‘010’) ITR3 (TS = ’011’) TIM4 TIM1 TIM2 TIM3 TIM8 TIM5 TIM2 TIM3 TIM4 TIM8 TIM9 TIM2 TIM3...
Page 441: Tim9/12 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0008 16.4.4 TIM9/12 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC2OF CC1OF CC2IF CC1IF Reserved Reserved Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:11 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input...
Page 442: Tim9/12 Event Generation Register (Timx_Egr)
RM0008 General-purpose timers (TIM9 to TIM14) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software.
Page 443 General-purpose timers (TIM9 to TIM14) RM0008 Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled.
Page 444: Tim9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0008 General-purpose timers (TIM9 to TIM14) 16.4.6 TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes.
Page 445 General-purpose timers (TIM9 to TIM14) RM0008 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively.
Page 446 RM0008 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1...
Page 447: Tim9/12 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM9 to TIM14) RM0008 16.4.7 TIM9/12 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC2NP CC2P CC2E CC1NP CC1P CC1E Reserved Res. Res. Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value.
Page 448: Tim9/12 Counter (Timx_Cnt)
RM0008 General-purpose timers (TIM9 to TIM14) Table 90. Output control bit for standard OCx channels CCxE bit OCx output state Output disabled (OCx=’0’, OCx_EN=’0’) OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers.
Page 449: Tim9/12 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0008 16.4.11 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit).
Page 450: Table 91. Tim9/12 Register Map And Reset Values
RM0008 General-purpose timers (TIM9 to TIM14) Table 91. TIM9/12 register map and reset values Offset Register TIMx_CR1 [1:0] 0x00 Reserved Reserved Reset value TIMx_SMCR TS[2:0] SMS[2:0] 0x08 Reserved Reset value TIMx_DIER 0x0C Reserved Reserved Reset value TIMx_SR 0x10 Reserved Reserved Reset value TIMx_EGR 0x14...
Page 451 General-purpose timers (TIM9 to TIM14) RM0008 Table 91. TIM9/12 register map and reset values (continued) Offset Register TIMx_CCR2 CCR2[15:0] 0x38 Reserved Reset value 0x3C to Reserved 0x4C Refer to Table 3 on page 51 for the register boundary addresses. 451/1128 DocID13902 Rev 15...
Page 452: Tim10/11/13/14 Registers
RM0008 General-purpose timers (TIM9 to TIM14) 16.5 TIM10/11/13/14 registers The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.5.1 TIM10/11/13/14 control register 1 (TIMx_CR1) Address offset: 0x00...
Page 453: Tim10/11/13/14 Status Register (Timx_Sr)
General-purpose timers (TIM9 to TIM14) RM0008 16.5.2 TIM10/11/13/14 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC1OF CC1IF Reserved Reserved rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 454: Tim10/11/13/14 Capture/Compare Mode Register 1
RM0008 General-purpose timers (TIM9 to TIM14) Bits 15:2 Reserved, must be kept at reset value. Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or is sent if enabled.
Page 455 General-purpose timers (TIM9 to TIM14) RM0008 Output compare mode Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 is derived.
Page 456 RM0008 General-purpose timers (TIM9 to TIM14) Input capture mode Bits 15:8 Reserved, must be kept at reset value. Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 457: Tim10/11/13/14 Capture/Compare Enable Register
General-purpose timers (TIM9 to TIM14) RM0008 16.5.5 TIM10/11/13/14 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 CC1NP CC1P CC1E Reserved Res. Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity. CC1 channel configured as output: CC1NP must be kept cleared.
Page 458: Tim10/11/13/14 Counter (Timx_Cnt)
RM0008 General-purpose timers (TIM9 to TIM14) 16.5.6 TIM10/11/13/14 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 CNT[15:0] Bits 15:0 CNT[15:0]: Counter value 16.5.7 TIM10/11/13/14 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1).
Page 459: Tim10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
General-purpose timers (TIM9 to TIM14) RM0008 16.5.9 TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 CCR1[15:0] Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 460 RM0008 General-purpose timers (TIM9 to TIM14) Table 93. TIM10/11/13/14 register map and reset values (continued) Offset Register TIMx_CCMR1 OC1M CC1S Output compare [2:0] [1:0] Reserved mode Reset value 0x18 TIMx_CCMR1 CC1S IC1F[3:0] Input capture [1:0] Reserved [1:0] mode Reset value 0x1C Reserved TIMx_CCER...
Page 461: Basic Timers (Tim6&Tim7)
Basic timers (TIM6&TIM7) RM0008 Basic timers (TIM6&TIM7) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 462: Tim6&Tim7 Functional Description
RM0008 Basic timers (TIM6&TIM7) Figure 169. Basic timer block diagram TRGO Trigger Internal clock (CK_INT) to DAC TIMxCLK from RCC controller Reset, Enable, Count, Controller Auto-reload Register Stop, Clear or up CK_PSC CK_CNT ± Prescaler COUNTER Flag Preload registers transferred to active registers on U event according to control bit event interrupt &...
Page 463: Figure 170. Counter Timing Diagram With Prescaler Division Change From 1 To 2
Basic timers (TIM6&TIM7) RM0008 Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.
Page 464: Counting Mode
RM0008 Basic timers (TIM6&TIM7) 17.3.2 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 465: Figure 173. Counter Timing Diagram, Internal Clock Divided By 2
Basic timers (TIM6&TIM7) RM0008 Figure 173. Counter timing diagram, internal clock divided by 2 CK_INT CNT_EN Timer clock = CK_CNT Counter register 0034 0035 0036 0000 0001 0002 0003 Counter overflow Update event (UEV) Update interrupt flag (UIF) Figure 174. Counter timing diagram, internal clock divided by 4 CK_INT CNT_EN TImer clock = CK_CNT...
Page 466: Clock Source
RM0008 Basic timers (TIM6&TIM7) Figure 176. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) CK_INT CNT_EN Timer clock = CK_CNT Counter register 32 33 34 35 36 01 02 03 04 05 06 07 Counter overflow Update event (UEV) Update interrupt flag (UIF) Auto-reload register...
Page 467: Debug Mode
Basic timers (TIM6&TIM7) RM0008 Figure 178. Control circuit in normal mode, internal clock divided by 1 CK_INT CEN=CNT_EN CNT_INIT Counter clock = CK_CNT = CK_PSC Counter register 32 33 34 35 36 01 02 03 04 05 06 07 17.3.4 Debug mode ®...
Page 468 RM0008 Basic timers (TIM6&TIM7) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: –...
Page 469: Tim6&Tim7 Control Register 2 (Timx_Cr2)
Basic timers (TIM6&TIM7) RM0008 17.4.2 TIM6&TIM7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 MMS[2:0] Reserved Reserved Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 470: Tim6&Tim7 Status Register (Timx_Sr)
RM0008 Basic timers (TIM6&TIM7) 17.4.4 TIM6&TIM7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 Reserved rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred.
Page 471: Tim6&Tim7 Prescaler (Timx_Psc)
Basic timers (TIM6&TIM7) RM0008 17.4.7 TIM6&TIM7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 PSC[15:0] Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to f / (PSC[15:0] + 1). CK_PSC PSC contains the value to be loaded into the active prescaler register at each update event. 17.4.8 TIM6&TIM7 auto-reload register (TIMx_ARR) Address offset: 0x2C...
Page 472: Tim6&Tim7 Register Map
RM0008 Basic timers (TIM6&TIM7) 17.4.9 TIM6&TIM7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: Table 94. TIM6&TIM7 register map and reset values Offset Register TIMx_CR1 0x00 Reserved Reset value TIMx_CR2 MMS[2:0] 0x04 Reserved Reset value 0x08...
Page 473: Real-Time Clock (Rtc)
Real-time clock (RTC) RM0008 Real-time clock (RTC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 474: Rtc Main Features
RM0008 Real-time clock (RTC) 18.2 RTC main features • Programmable prescaler: division factor up to 2 • 32-bit programmable counter for long-term measurement • Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least four times slower than the PCLK1 clock) •...
Page 475: Rtc Functional Description
Real-time clock (RTC) RM0008 18.3 RTC functional description 18.3.1 Overview The RTC consists of two main units (see Figure 179 on page 475). The first one (APB1 Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit registers accessible from the APB1 bus in read or write mode (for more information refer to Section 18.4: RTC registers on page 478).
Page 476: Resetting Rtc Registers
RM0008 Real-time clock (RTC) 18.3.2 Resetting RTC registers All system registers are asynchronously reset by a System Reset or Power Reset, except for RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV. The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup Domain reset.
Page 477: Rtc Flag Assertion
Real-time clock (RTC) RM0008 18.3.5 RTC flag assertion The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update of the RTC Counter. The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the counter reaches 0x0000.
Page 478: Rtc Registers
RM0008 Real-time clock (RTC) 18.4 RTC registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 18.4.1 RTC control register high (RTC_CRH) Address offset: 0x00 Reset value: 0x0000 OWIE...
Page 479: Rtc Control Register Low (Rtc_Crl)
Real-time clock (RTC) RM0008 18.4.2 RTC control register low (RTC_CRL) Address offset: 0x04 Reset value: 0x0020 RTOFF ALRF SECF Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:6 Reserved, forced by hardware to 0. Bit 5 RTOFF: RTC operation OFF With this bit the RTC reports the status of the last write operation performed on its registers, indicating if it has been completed or not.
Page 480: Rtc Prescaler Load Register (Rtc_Prlh / Rtc_Prll)
RM0008 Real-time clock (RTC) The functions of the RTC are controlled by this control register. It is not possible to write to the RTC_CR register while the peripheral is completing a previous write operation (flagged by RTOFF=0, see Section 18.3.4 on page 476).
Page 481: Rtc Prescaler Divider Register (Rtc_Divh / Rtc_Divl)
Real-time clock (RTC) RM0008 RTC prescaler load register low (RTC_PRLL) Address offset: 0x0C Write only (see Section 18.3.4 on page 476) Reset value: 0x8000 PRL[15:0] Bits 15:0 PRL[15:0]: RTC prescaler reload value low These bits are used to define the counter clock frequency according to the following formula: /(PRL[19:0]+1) TR_CLK RTCCLK...
Page 482: Rtc Counter Register (Rtc_Cnth / Rtc_Cntl)
RM0008 Real-time clock (RTC) 18.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers; the count rate is based on the TR_CLK time reference, generated by the prescaler. RTC_CNT registers keep the counting value of this counter. They are write-protected by bit RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 483: Rtc Alarm Register High (Rtc_Alrh / Rtc_Alrl)
Real-time clock (RTC) RM0008 18.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) When the programmable counter reaches the 32-bit value stored in the RTC_ALR register, an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’.
Page 484: Rtc Register Map
RM0008 Real-time clock (RTC) 18.4.7 RTC register map RTC registers are mapped as 16-bit addressable registers as described in the table below: Table 95. register map and reset values Offset Register RTC_CRH 0x00 Reserved 0 0 0 Reset value RTC_CRL 0x04 Reserved 1 0 0 0 0 0...
Page 485: Independent Watchdog (Iwdg)
Independent watchdog (IWDG) RM0008 Independent watchdog (IWDG) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 486: Hardware Watchdog
RM0008 Independent watchdog (IWDG) Whenever the key value 0xAAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. 19.3.1 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and will generate a reset unless the Key register is written by the software before the counter reaches end of count.
Page 487: Iwdg Registers
Independent watchdog (IWDG) RM0008 Table 96. Min/max IWDG timeout period at 40 kHz (LSI) (continued) Min timeout (ms) RL[11:0]= Max timeout (ms) RL[11:0]= Prescaler divider PR[2:0] bits 0x000 0xFFF /128 13107.2 /256 6 (or 7) 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz.
Page 488: Prescaler Register (Iwdg_Pr)
RM0008 Independent watchdog (IWDG) 19.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PR[2:0] Reserved Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected seeSection...
Page 489 Independent watchdog (IWDG) RM0008 Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 RVU PVU Reserved Bits 31:2 Reserved, must be kept at reset value. Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing.
Page 490: Iwdg Register Map
RM0008 Independent watchdog (IWDG) 19.4.5 IWDG register map The following table gives the IWDG register map and reset values. Table 97. IWDG register map and reset values Offset Register IWDG_KR KEY[15:0] Reserved 0x00 Reset value IWDG_PR PR[2:0] Reserved 0x04 Reset value IWDG_RLR RL[11:0] Reserved...
Page 491: Window Watchdog (Wwdg)
Window watchdog (WWDG) RM0008 Window watchdog (WWDG) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 492: Figure 183. Watchdog Block Diagram
RM0008 Window watchdog (WWDG) Figure 183. Watchdog block diagram Watchdog configuration register (WWDG_CFR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR Watchdog control register (WWDG_CR) WDGA 6-bit downcounter (CNT) PCLK1 (from RCC clock controller) WDG prescaler (WDGTB) The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.
Page 493: How To Program The Watchdog Timeout
Window watchdog (WWDG) RM0008 case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g.
Page 494: Debug Mode
RM0008 Window watchdog (WWDG) Table 98. Min-max timeout value @36 MHz (f PCLK1 Prescaler WDGTB Min timeout value Max timeout value 113 µs 7.28 ms 227 µs 14.56 ms 455 µs 29.12 ms 910 µs 58.25 ms 20.5 Debug mode ®...
Page 495: Wwdg Registers
Window watchdog (WWDG) RM0008 20.6 WWDG registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 20.6.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F Reserved...
Page 496: Configuration Register (Wwdg_Cfr)
RM0008 Window watchdog (WWDG) 20.6.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F Reserved WDGTB[1:0] W[6:0] Reserved Bit 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset.
Page 497: Wwdg Register Map
Window watchdog (WWDG) RM0008 20.6.4 WWDG register map The following table gives the WWDG register map and reset values. Table 99. WWDG register map and reset values Offset Register WWDG_CR T[6:0] 0x00 Reserved Reset value WWDG_CFR W[6:0] 0x04 Reserved Reset value WWDG_SR 0x08 Reserved...
Page 498: Flexible Static Memory Controller (Fsmc)
RM0008 Flexible static memory controller (FSMC) Flexible static memory controller (FSMC) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 32 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 499: Block Diagram
Flexible static memory controller (FSMC) RM0008 The FSMC has the following main features: • Interfaces with static memory-mapped devices including: – Static random access memory (SRAM) – NOR Flash memory – PSRAM (4 memory banks) • Two banks of NAND Flash with ECC hardware that checks up to 8 Kbytes of data •...
Page 500: Ahb Interface
RM0008 Flexible static memory controller (FSMC) Figure 185. FSMC block diagram 21.3 AHB interface The AHB slave interface enables internal CPUs and other bus master peripherals to access the external static memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16 or 8 bits wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 501: Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0008 The effect of this AHB error depends on the AHB master which has attempted the R/W access: ® • If it is the Cortex -M3 CPU, a hard fault interrupt is generated • If is a DMA, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.
Page 502: External Device Address Mapping
RM0008 Flexible static memory controller (FSMC) 21.4 External device address mapping From the FSMC point of view, the external memory is divided into 4 fixed-size banks of 256 Mbytes each (Refer to Figure 186): • Bank 1 used to address up to 4 NOR Flash or PSRAM memory devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows: –...
Page 503: Nand/Pc Card Address Mapping
Flexible static memory controller (FSMC) RM0008 Table 100. NOR/PSRAM bank selection (continued) HADDR[27:26] Selected bank Bank 1 - NOR/PSRAM 3 Bank 1 - NOR/PSRAM 4 1. HADDR are internal AHB address lines that are translated to external memory. HADDR[25:0] contain the external memory address. Since HADDR is a byte address whereas the memory is addressed in words, the address actually issued to the memory varies according to the memory data width, as shown in the following table.
Page 504: Nor Flash/Psram Controller
RM0008 Flexible static memory controller (FSMC) Table 103. NAND bank selections Section name HADDR[17:16] Address range Address section 0x020000-0x03FFFF Command section 0x010000-0x01FFFF Data section 0x000000-0x0FFFF The application software uses the 3 sections to access the NAND Flash memory: • To send a command to NAND Flash memory: the software must write the command value to any memory location in the command section.
Page 505: External Memory Interface Signals
Flexible static memory controller (FSMC) RM0008 Table 104. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Max. Address Duration of the address AHB clock cycle Asynchronous setup setup phase (HCLK) Duration of the address hold Asynchronous, AHB clock cycle Address hold phase muxed I/Os...
Page 506: Supported Memories And Transactions
RM0008 Flexible static memory controller (FSMC) NOR Flash, multiplexed I/Os Table 106. Multiplexed I/O NOR Flash FSMC signal name Function Clock (for synchronous access) A[25:16] Address bus AD[15:0] 16-bit multiplexed, bidirectional address/data bus NE[x] Chip select, x = 1..4 Output enable Write enable Latch enable (this signal is called address valid, NADV, by some NOR NL(=NADV)
Page 507: Table 108. Nor Flash/Psram Controller: Example Of Supported Memories
Flexible static memory controller (FSMC) RM0008 Table 108. NOR Flash/PSRAM controller: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous R Asynchronous W Asynchronous R Asynchronous W NOR Flash Asynchronous R Split into 2 FSMC accesses (muxed I/Os Asynchronous W Split into 2 FSMC accesses...
Page 508: General Timing Rules
RM0008 Flexible static memory controller (FSMC) 21.5.3 General timing rules Signals synchronization • All controller output signals change on the rising edge of the internal clock (HCLK) • In synchronous mode (read or write), all output signals change on the rising edge of HCLK.
Page 509: Figure 187. Mode1 Read Accesses
Flexible static memory controller (FSMC) RM0008 Figure 187. Mode1 read accesses Memory transaction A[25:0] NBL[1:0] High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles Data sampled Data strobe ai14720c 1. NBL[1:0] are driven low during read access. Figure 188.
Page 510: Table 109. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 109. FSMC_BCRx bit fields Bit name Value to set number 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved Set to 1 if the memory supports this feature. Otherwise keep at ASYNCWAIT EXTMOD WAITEN...
Page 511: Figure 189. Modea Read Accesses
Flexible static memory controller (FSMC) RM0008 Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 189. ModeA read accesses Memory transaction A[25:0] NBL[1:0] High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles Data sampled Data strobe ai14722c...
Page 512: Table 111. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) The differences compared with mode1 are the toggling of NOE and the independent read and write timings. Table 111. FSMC_BCRx bit fields Bit name Value to set number 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved Set to 1 if the memory supports this feature.
Page 513: Table 113. Fsmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 113. FSMC_BWTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for read accesses).
Page 514: Figure 192. Mode2 Write Accesses
RM0008 Flexible static memory controller (FSMC) Figure 192. Mode2 write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14723b Figure 193. Mode B write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0]...
Page 515: Table 114. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 114. FSMC_BCRx bit fields Bit name Value to set number 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved Set to 1 if the memory supports this feature. Otherwise keep at ASYNCWAIT EXTMOD 0x1 for mode B, 0x0 for mode 2...
Page 516: Table 116. Fsmc_Bwtrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 116. FSMC_BWTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+1 HCLK cycles for write accesses, DATAST+3 HCLK cycles for write accesses).
Page 517: Table 117. Fsmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Figure 195. Mode C write accesses Memory transaction A[25:0] NADV 1HCLK D[15:0] data driven by FSMC (ADDSET +1) (DATAST + 1) HCLK cycles HCLK cycles ai14723b The differences compared with mode1 are the toggling of NOE and the independent read and write timings.
Page 518: Table 118. Fsmc_Btrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 117. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set MUXEN MBKEN Table 118. FSMC_BTRx bit fields Bit name Value to set number 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT 23-20 CLKDIV 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Page 519: Figure 196. Mode D Read Accesses
Flexible static memory controller (FSMC) RM0008 Mode D - asynchronous access with extended address Figure 196. Mode D read accesses Memory transaction A[25:0] NADV High data driven D[15:0] by memory (ADDSET +1) (DATAST + 1) 2 HCLK HCLK cycles HCLK cycles cycles (ADDHLD + 1) HCLK cycles...
Page 520: Table 120. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Table 120. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-20 Reserved 0x000 CBURSTRW 0x0 (no effect on asynchronous mode) 18:16 Reserved Set to 1 if the memory supports this feature. Otherwise keep ASYNCWAIT at 0.
Page 521: Table 122. Fsmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 122. FSMC_BWTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT 23-20 CLKDIV 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST+3 HCLK cycles) for 15-8 DATAST write accesses.
Page 522: Table 123. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 198. Multiplexed write accesses Memory transaction A[25:16] NADV 1HCLK AD[15:0] Lower address data driven by FSMC (ADDSET +1) ADDHLD (DATAST + 2) HCLK cycles HCLK cycles HCLK cycles ai14729c The difference with mode D is the drive of the lower address byte(s) on the databus. Table 123.
Page 523: Table 124. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 123. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set MUXEN MBKEN Table 124. FSMC_BTRx bit fields Bit No. Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care...
Page 524: Figure 199. Asynchronous Wait During A Read Access
RM0008 Flexible static memory controller (FSMC) Memory asserts the WAIT signal aligned to NOE/NWE which toggles: ≥ × DATAST HCLK max_wait_assertion_time Memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then ≥ × –...
Page 525: Figure 200. Asynchronous Wait During A Write Access
Flexible static memory controller (FSMC) RM0008 Figure 200. Asynchronous wait during a write access 1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register. 525/1128 DocID13902 Rev 15...
Page 526: Synchronous Transactions
RM0008 Flexible static memory controller (FSMC) 21.5.5 Synchronous transactions The memory clock, CLK, is a submultiple of HCLK according to the value of parameter CLKDIV. NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FSMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion).
Page 527: Figure 201. Wait Configurations
Flexible static memory controller (FSMC) RM0008 During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the chip select and output enable signals valid, and does not consider the data valid. There are two timing configurations for the NOR Flash NWAIT signal in burst mode: •...
Page 528: Table 125. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM) 1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. 2.
Page 529: Table 126. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 125. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set WRAPMOD WAITPOL to be set according to memory BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN...
Page 530: Table 127. Fsmc_Bcrx Bit Fields
RM0008 Flexible static memory controller (FSMC) Figure 203. Synchronous multiplexed write mode - PSRAM (CRAM) 1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. NWAIT polarity is set to 0. 3. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 127.
Page 531: Table 128. Fsmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0008 Table 127. FSMC_BCRx bit fields (continued) Bit No. Bit name Value to set WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP MUXEN...
Page 532: Nor/Psram Control Registers
RM0008 Flexible static memory controller (FSMC) 21.5.6 NOR/PSRAM control registers The NOR/PSRAM control registers have to be accessed by words (32 bits). SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCR1..4) Address offset: 0xA000 0000 + 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
Page 533 Flexible static memory controller (FSMC) RM0008 Bit 13 WAITEN: Wait enable bit. This bit enables/disables wait-state insertion via the NWAIT signal when accessing the Flash memory in synchronous mode. 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed Flash latency period) 1: NWAIT signal is enabled (its level is taken into account after the programmed Flash latency period to insert wait states if asserted) (default after reset)
Page 534 RM0008 Flexible static memory controller (FSMC) Bits 3:2 MTYP: Memory type. Defines the type of external memory attached to the corresponding memory bank: 00: SRAM (default after reset for Bank 2...4) 01: PSRAM (CRAM) 10: NOR Flash(default after reset for Bank 1) 11: reserved Bit 1 MUXEN: Address/data multiplexing enable bit.
Page 535 Flexible static memory controller (FSMC) RM0008 SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTR1..4) Address offset: 0xA000 0000 + 0x04 + 8 * (x – 1), x = 1..4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FSMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses...
Page 536 RM0008 Flexible static memory controller (FSMC) Bits 15:8 DATAST: Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure 187 Figure 198), used in asynchronous accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 × HCLK clock cycles 0000 0010: DATAST phase duration = 3 ×...
Page 537 Flexible static memory controller (FSMC) RM0008 SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTR1..4) Address offset: 0xA000 0000 + 0x104 + 8 * (x – 1), x = 1...4 Reset value: 0x0FFF FFFF This register contains the control information of each memory bank, used for SRAMs, PSRAMs and NOR Flash memories.
Page 538: Nand Flash/Pc Card Controller
RM0008 Flexible static memory controller (FSMC) Bits 15:8 DATAST: Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 187 Figure 198), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: 0000 0000: Reserved 0000 0001: DATAST phase duration = 2 ×...
Page 539: External Memory Interface Signals
Flexible static memory controller (FSMC) RM0008 Table 129. Programmable NAND/PC Card access parameters Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) Memory setup AHB clock cycle to set up the address before the Read/Write time (HCLK) command assertion Minimum duration (HCLK clock AHB clock cycle...
Page 540: Table 131. 16-Bit Nand Flash
RM0008 Flexible static memory controller (FSMC) 16-bit NAND Flash Table 131. 16-bit NAND Flash FSMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus NCE[x] Chip select, x = 2, 3 NOE(= NRE)
Page 541: Nand Flash / Pc Card Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0008 21.6.2 NAND Flash / PC Card supported memories and transactions Table 133 below shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash / PC Card controller appear in gray.
Page 542: Nand Flash Operations
RM0008 Flexible static memory controller (FSMC) Figure 204. NAND/PC Card controller timing for common memory access HCLK Address NCEx High NREG, NIOW, NIOR MEMxSET + 1 MEMxWAIT + 1 MEMxHOLD + 1 NWE, MEMxHIZ write_data read_data Valid ai14732d 1. NOE remains high (inactive) during write access. NWE remains high (inactive) during read access. 2.
Page 543: Nand Flash Pre-Wait Functionality
Flexible static memory controller (FSMC) RM0008 the NAND Flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FSMC, which can be used to implement the prewait functionality needed by some NAND Flash memories (see details in Section 21.6.5: NAND Flash pre-wait...
Page 544: Computation Of The Error Correction Code (Ecc) In Nand Flash Memory
RM0008 Flexible static memory controller (FSMC) timing definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > t max). This guarantees that NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where NCE is not don’t care).
Page 545: Pc Card/Compactflash Operations
Flexible static memory controller (FSMC) RM0008 Enable the ECCEN bit in the FSMC_PCR2/3 register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FSMC_ECCR2/3 register and store it in a variable.
Page 546: Table 134. 16-Bit Pc-Card Signals And Access Type
RM0008 Flexible static memory controller (FSMC) transfers at even addresses: nCE1 will be asserted low, NCE2 will be asserted high and only the even bytes will be valid. • Accesses to I/O Space can be performed either through AHB 8-bit or 16-bit accesses. Table 134.
Page 547: Nand Flash/Pc Card Control Registers
Flexible static memory controller (FSMC) RM0008 xxWAITx >= 4 + max_wait_assertion_time/HCLK Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once nOE/nWE or nIORD/nIOWR is low. After the de-assertion of nWAIT, the FSMC extends the WAIT phase for 4 HCLK clock cycles.
Page 548 RM0008 Flexible static memory controller (FSMC) Bits 5:4 PWID: Databus width. Defines the external memory device width. 00: 8 bits 01: 16 bits (default after reset). This value is mandatory for PC Cards. 10: reserved, do not use 11: reserved, do not use Bit 3 PTYP: Memory type.
Page 549 Flexible static memory controller (FSMC) RM0008 Bits 31:7 Reserved, must be kept at reset value. Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit 0: Interrupt falling edge detection request disabled 1: Interrupt falling edge detection request enabled Bit 4...
Page 550 RM0008 Flexible static memory controller (FSMC) Bits 31:24 MEMHIZx: Common memory x databus HiZ time Defines the number of HCLK (+1 only for NAND) clock cycles during which the databus is kept in HiZ after the start of a PC Card/NAND Flash write access to common memory space on socket x.
Page 551 Flexible static memory controller (FSMC) RM0008 Bits 31:24 ATTHIZx: Attribute memory x databus HiZ time Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a PC CARD/NAND Flash write access to attribute memory space on socket x. Only valid for write transaction: 0000 0000: 0 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset)
Page 552 RM0008 Flexible static memory controller (FSMC) Bits 31:24 IOHIZx: I/O x databus HiZ time Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the start of a PC Card write access to I/O space on socket x. Only valid for write transaction: 0000 0000: 0 HCLK cycle 1111 1111: 255 HCLK cycles (default value after reset) Bits 23:16 IOHOLDx: I/O x hold time...
Page 553: Table 135. Ecc Result Relevant Bits
Flexible static memory controller (FSMC) RM0008 Bits 31:0 ECCx: ECC result This field provides the value computed by the ECC computation logic. Table 135 hereafter describes the contents of these bit fields. Table 135. ECC result relevant bits ECCPS[2:0] Page size in bytes ECC bits ECC[21:0] ECC[23:0]...
Page 554: Fsmc Register Map
RM0008 Flexible static memory controller (FSMC) 21.6.9 FSMC register map The following table summarizes the FSMC registers. Table 136. FSMC register map Offset Register 0000 FSMC_BCR1 Reserved Reserved 0008 FSMC_BCR2 Reserved Reserved 0010 FSMC_BCR3 Reserved Reserved 0018 FSMC_BCR4 Reserved Reserved 0004 FSMC_BTR1 Res.
Page 555 Flexible static memory controller (FSMC) RM0008 Table 136. FSMC register map (continued) Offset Register 0xA000 FSMC_PMEM4 MEMHIZx MEMHOLDx MEMWAITx MEMSETx 00A8 0xA000 FSMC_PATT2 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 006C 0xA000 FSMC_PATT3 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 008C 0xA000 FSMC_PATT4 ATTHIZx ATTHOLDx ATTWAITx ATTSETx 00AC 0xA000...
Page 556: Secure Digital Input/Output Interface (Sdio)
RM0008 Secure digital input/output interface (SDIO) Secure digital input/output interface (SDIO) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 557: Sdio Bus Topology
Secure digital input/output interface (SDIO) RM0008 interface using a protocol that utilizes the existing MMC access primitives. The interface electrical and signaling definition is as defined in the MMC reference. The MultiMediaCard/SD bus connects cards to the controller. The current version of the SDIO supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous.
Page 558: Figure 208. Sdio (Multiple) Block Write Operation
RM0008 Secure digital input/output interface (SDIO) Figure 208. SDIO (multiple) block write operation From host to card From card to host Stop command stops data transfer Data from host to card Command Response Command Response SDIO_CMD SDIO_D Busy Data block crc Data block crc Busy Busy...
Page 559: Sdio Functional Description
Secure digital input/output interface (SDIO) RM0008 22.3 SDIO functional description The SDIO consists of two parts: • The SDIO adapter block provides all functions specific to the MMC/SD/SD I/O card such as the clock generation unit, command and data transfer. •...
Page 560: Sdio Adapter
RM0008 Secure digital input/output interface (SDIO) Table 137. SDIO I/O definitions Direction Description MultiMediaCard/SD/SDIO card clock. This pin is the clock from SDIO_CK Output host to card. MultiMediaCard/SD/SDIO card command. This pin is the SDIO_CMD Bidirectional bidirectional command/response signal. MultiMediaCard/SD/SDIO card data. These pins are the SDIO_D[7:0] Bidirectional bidirectional databus.
Page 561: Figure 213. Control Unit
Secure digital input/output interface (SDIO) RM0008 Control unit The control unit contains the power management functions and the clock divider for the memory card clock. There are three power phases: • power-off • power-up • power-on Figure 213. Control unit Control unit Power management Clock...
Page 562: Figure 214. Sdio Adapter Command Path
RM0008 Secure digital input/output interface (SDIO) Figure 214. SDIO adapter command path Status Control Command To control unit flag logic timer Adapter registers SDIO_CMDin Argument SDIO_CMDout Shift register To AHB interface Response registers ai14805 • Command path state machine (CPSM) –...
Page 563: Figure 215. Command Path State Machine (Cpsm)
Secure digital input/output interface (SDIO) RM0008 Figure 215. Command path state machine (CPSM) CE-ATA Command On reset Completion signal Wait_CPL received or CPSM disabled or Command CRC failed CPSM Enabled and Idle Response received or Response Received in CE-ATA pending command disabled or command mode and no interrupt and CRC failed...
Page 564: Table 138. Command Format
RM0008 Secure digital input/output interface (SDIO) Figure 216. SDIO command transfer at least 8 SDIO_CK cycles Command Response Command SDIO_CK State Idle Send Wait Receive Idle Send SDIO_CMD Hi-Z Controller drives Hi-Z Card drives Hi-Z Controller drives ai14707 • Command format –...
Page 565: Table 139. Short Response Format
Secure digital input/output interface (SDIO) RM0008 Table 139. Short response format Bit position Width Value Description Start bit Transmission bit [45:40] Command index [39:8] Argument [7:1] CRC7(or 1111111) End bit Table 140. Long response format Bit position Width Value Description Start bit Transmission bit [133:128]...
Page 566: Figure 217. Data Path
RM0008 Secure digital input/output interface (SDIO) Data path The data path subunit transfers data to and from cards. Figure 217 shows a block diagram of the data path. Figure 217. Data path Data path Status Control Data To control unit flag logic timer...
Page 567: Figure 218. Data Path State Machine (Dpsm)
Secure digital input/output interface (SDIO) RM0008 Figure 218. Data path state machine (DPSM) On reset DPSM disabled DPSM enabled and Read Wait Read Wait Started and SD I/O mode enabled Disabled or FIFO underrun or Idle end of data or CRC fail Disabled or CRC fail or timeout Enable and not send...
Page 568: Table 142. Data Token Format
RM0008 Secure digital input/output interface (SDIO) Note: The DPSM remains in the Wait_S state for at least two clock periods to meet the N timing requirements, where N is the number of clock cycles between the reception of the card response and the start of the data transfer from the host.
Page 569: Table 143. Transmit Fifo Status Flags
Secure digital input/output interface (SDIO) RM0008 Depending on the TXACT and RXACT flags, the FIFO can be disabled, transmit enabled, or receive enabled. TXACT and RXACT are driven by the data path subunit and are mutually exclusive: – The transmit FIFO refers to the transmit logic and data buffer when TXACT is asserted –...
Page 570: Sdio Ahb Interface
RM0008 Secure digital input/output interface (SDIO) Table 144. Receive FIFO status flags Flag Description RXFIFOF Set to high when all 32 receive FIFO words contain valid data RXFIFOE Set to high when the receive FIFO does not contain valid data. Set to high when 8 or more receive FIFO words contain valid data.
Page 571: Card Functional Description
Secure digital input/output interface (SDIO) RM0008 Do the card identification process Increase the SDIO_CK frequency Select the card by sending CMD7 Configure the DMA2 as follows: Enable DMA2 controller and clear any pending interrupts Program the DMA2_Channel4 source address register with the memory location’s base address and DMA2_Channel4 destination address register with the SDIO_FIFO register address Program DMA2_Channel4 control register (memory increment, not peripheral...
Page 572: Operating Voltage Range Validation
RM0008 Secure digital input/output interface (SDIO) 22.4.3 Operating voltage range validation All cards can communicate with the SDIO card host using any operating voltage within the specification range. The supported minimum and maximum V values are defined in the operation conditions register (OCR) on the card. Cards that store the card identification number (CID) and card specific data (CSD) in the payload memory are able to communicate this information only under data-transfer V conditions.
Page 573: Block Write
Secure digital input/output interface (SDIO) RM0008 The bus is activated. The SDIO card host broadcasts SD_APP_OP_COND (ACMD41). The cards respond with the contents of their operation condition registers. The incompatible cards are placed in the inactive state. The SDIO card host broadcasts ALL_SEND_CID (CMD2) to all active cards. The cards send back their unique card identification numbers (CIDs) and enter the Identification state.
Page 574: Block Read
RM0008 Secure digital input/output interface (SDIO) select a different card), which will place the card in the Disconnect state and release the SDIO_D line(s) without interrupting the write operation. When reselecting the card, it will reactivate busy indication by pulling SDIO_D to low if programming is still in progress and the write buffer is unavailable.
Page 575 Secure digital input/output interface (SDIO) RM0008 The maximum clock frequency for a stream write operation is given by the following equation fields of the card-specific data register: 8 2 writebllen × ) NSAC – ( Maximumspeed MIN TRANSPEED ------------------------------------------------------------------------ × TAAC R2WFACTOR •...
Page 576: Erase: Group Erase And Sector Erase
RM0008 Secure digital input/output interface (SDIO) Stream read (MultiMediaCard only) READ_DAT_UNTIL_STOP (CMD11) controls a stream-oriented data transfer. This command instructs the card to send its data, starting at a specified address, until the SDIO card host sends STOP_TRANSMISSION (CMD12). The stop command has an execution delay due to the serial command transmission and the data transfer stops after the end bit of the stop command.
Page 577: Wide Bus Selection Or Deselection
Secure digital input/output interface (SDIO) RM0008 The card indicates that an erase is in progress by holding SDIO_D low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the card. 22.4.9 Wide bus selection or deselection Wide bus (4-bit bus width) operation mode is selected or deselected using SET_BUS_WIDTH (ACMD6).
Page 578 RM0008 Secure digital input/output interface (SDIO) the card must be selected before using it. The card lock/unlock commands have the structure and bus transaction types of a regular single-block write command. The transferred data block includes all of the required information for the command (the password setting mode, the PWD itself, and card lock/unlock).
Page 579 Secure digital input/output interface (SDIO) RM0008 Resetting the password Select a card (SELECT/DESELECT_CARD, CMD7), if none is already selected. Define the block length (SET_BLOCKLEN, CMD16) to send, given by the 8-bit card lock/unlock mode, the 8-bit PWD_LEN, and the number of bytes in the currently used password.
Page 580: Card Status Register
RM0008 Secure digital input/output interface (SDIO) The unlocking function is only valid for the current power session. When the PWD field is not clear, the card is locked automatically on the next power-up. An attempt to unlock an unlocked card fails and the LOCK_UNLOCK_FAILED error bit is set in the card status register.
Page 581: Table 145. Card Status
Secure digital input/output interface (SDIO) RM0008 Table 145. Card status Clear Bits Identifier Type Value Description condition The command address argument was out of the allowed range for this card. ’0’= no error ADDRESS_ A multiple block or stream read/write E R X OUT_OF_RANGE ’1’= error...
Page 582 RM0008 Secure digital input/output interface (SDIO) Table 145. Card status (continued) Clear Bits Identifier Type Value Description condition (Undefined by the standard) A generic ’0’= no error card error related to the (and detected ERROR ’1’= error during) execution of the last host command (e.g.
Page 583: Sd Status Register
Secure digital input/output interface (SDIO) RM0008 Table 145. Card status (continued) Clear Bits Identifier Type Value Description condition ’0’= no error Error in the sequence of the AKE_SEQ_ERROR ’1’= error authentication process Reserved for application specific commands Reserved for manufacturer test mode 22.4.12 SD status register The SD status contains status bits that are related to the SD memory card proprietary...
Page 584 RM0008 Secure digital input/output interface (SDIO) Table 146. SD status (continued) Clear Bits Identifier Type Value Description condition In the future, the 8 LSBs will ’00xxh’= SD Memory Cards as be used to define different defined in Physical Spec Ver1.01- variations of an SD memory 2.00 (’x’= don’t care).
Page 585: Table 147. Speed Class Code Field
Secure digital input/output interface (SDIO) RM0008 Table 147. Speed class code field SPEED_CLASS Value definition Class 0 Class 2 Class 4 Class 6 04h – FFh Reserved PERFORMANCE_MOVE This 8-bit field indicates Pm (performance move) and the value can be set by 1 [MB/sec] steps.
Page 586: Table 149. Au_Size Field
RM0008 Secure digital input/output interface (SDIO) Table 149. AU_SIZE field (continued) AU_SIZE Value definition 4 MB Ah – Fh Reserved The maximum AU size, which depends on the card capacity, is defined in Table 150. The card can be set to any AU size between RU size and maximum AU size. Table 150.
Page 587: Sd I/O Mode
Secure digital input/output interface (SDIO) RM0008 Table 152. Erase timeout field (continued) ERASE_TIMEOUT Value definition --------- --------- 63 [sec] ERASE_OFFSET This 2-bit field indicates T and one of four values can be selected. This field is OFFSET meaningless if the ERASE_SIZE and ERASE_TIMEOUT fields are set to 0. Table 153.
Page 588: Commands And Responses
RM0008 Secure digital input/output interface (SDIO) suspend/resume operation on the MMC/SD bus, the MMC/SD module performs the following steps: Determines the function currently using the SDIO_D [3:0] line(s) Requests the lower-priority or slower transaction to suspend Waits for the transaction suspension to complete Begins the higher-priority transaction Waits for the completion of the higher priority transaction Restores the suspended transaction...
Page 589: Table 154. Block-Oriented Write Commands
Secure digital input/output interface (SDIO) RM0008 The bus transaction for a GEN_CMD is the same as the single-block read or write commands (WRITE_BLOCK, CMD24 or READ_SINGLE_BLOCK,CMD17). In this case, the argument denotes the direction of the data transfer rather than the address, and the data block has vendor-specific format and meaning.
Page 590: Table 155. Block-Oriented Write Protection Commands
RM0008 Secure digital input/output interface (SDIO) Table 155. Block-oriented write protection commands Response Type Argument Abbreviation Description index format If the card has write protection features, this command sets the write protection bit [31:0] data CMD28 ac of the addressed group. The properties of SET_WRITE_PROT address write protection are coded in the card-...
Page 591: Response Formats
Secure digital input/output interface (SDIO) RM0008 Table 157. I/O mode commands (continued) Response Type Argument Abbreviation Description index format CMD40 bcr [31:0] stuff bits GO_IRQ_STATE Places the system in the interrupt mode. CMD41 Reserved Table 158. Lock card Response Type Argument Abbreviation Description...
Page 592: R1 (Normal Response Command)
RM0008 Secure digital input/output interface (SDIO) 22.5.1 R1 (normal response command) Code length = 48 bits. The 45:40 bits indicate the index of the command to be responded to, this value being interpreted as a binary-coded number (between 0 and 63). The status of the card is coded in 32 bits.
Page 593: R4 (Fast I/O)
Secure digital input/output interface (SDIO) RM0008 Table 162. R3 response Bit position Width (bits Value Description Start bit Transmission bit [45:40] ‘111111’ Reserved [39:8] OCR register [7:1] ‘1111111’ Reserved End bit 22.5.5 R4 (Fast I/O) Code length: 48 bits. The argument field contains the RCA of the addressed card, the register address to be read out or written to, and its content.
Page 594: R5 (Interrupt Request)
RM0008 Secure digital input/output interface (SDIO) Table 164. R4b response (continued) Bit position Width (bits Value Description [7:1] Reserved End bit Once an SD I/O card has received a CMD5, the I/O portion of that card is enabled to respond normally to all further commands. This I/O enable of the function within the I/O card will remain set until a reset, power cycle or CMD52 with write to I/O reset is received by the card.
Page 595: Sdio I/O Card-Specific Operations
Secure digital input/output interface (SDIO) RM0008 Table 166. R6 response (continued) Bit position Width (bits) Value Description [31:16] RCA [31:16] of winning card or of the host [39:8] Argument field [15:0] Not defined. May be used for IRQ data [7:1] CRC7 End bit The card [23:8] status bits are changed when CMD3 is sent to an I/O-only card.
Page 596: Sdio Suspend/Resume Operation
RM0008 Secure digital input/output interface (SDIO) As SDIO_CK is stopped, any command can be issued to the card. During a read/wait interval, the SDIO can detect SDIO interrupts on SDIO_D1. 22.6.3 SDIO suspend/resume operation While sending data to the card, the SDIO can suspend the write operation. the SDIO_CMD[11] bit is set and indicates to the CPSM that the current command is a suspend command.
Page 597: Ce-Ata Interrupt
Secure digital input/output interface (SDIO) RM0008 When ‘0’ is received on the CMD line, the CPSM enters the Idle state. No new command can be sent for 7 bit cycles. Then, for the last 5 cycles (out of the 7) the CMD line is driven to ‘1’...
Page 598: Sdio Power Control Register (Sdio_Power)
RM0008 Secure digital input/output interface (SDIO) 22.9.1 SDIO power control register (SDIO_POWER) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PWRC Reserved rw rw...
Page 599: Sdio Argument Register (Sdio_Arg)
Secure digital input/output interface (SDIO) RM0008 Bit 10 BYPASS: Clock divider bypass enable bit 0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal. 1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal. Bit 9 PWRSAV: Power saving configuration bit For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting PWRSAV:...
Page 600: Sdio Command Register (Sdio_Cmd)
RM0008 Secure digital input/output interface (SDIO) 22.9.4 SDIO command register (SDIO_CMD) Address offset: 0x0C Reset value: 0x0000 0000 The SDIO_CMD register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM).
Page 601: Sdio Command Response Register (Sdio_Respcmd)
Secure digital input/output interface (SDIO) RM0008 argument can vary according to the type of response: the software will distinguish the type of response according to the sent command. CE-ATA devices send only short responses. 22.9.5 SDIO command response register (SDIO_RESPCMD) Address offset: 0x10 Reset value: 0x0000 0000 The SDIO_RESPCMD register contains the command index field of the last command...
Page 602: Sdio Data Timer Register (Sdio_Dtimer)
RM0008 Secure digital input/output interface (SDIO) 22.9.7 SDIO data timer register (SDIO_DTIMER) Address offset: 0x24 Reset value: 0x0000 0000 The SDIO_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDIO_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state.
Page 603: Sdio Data Control Register (Sdio_Dctrl)
Secure digital input/output interface (SDIO) RM0008 22.9.9 SDIO data control register (SDIO_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDIO_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DBLOCKSIZE Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 604: Sdio Data Counter Register (Sdio_Dcount)
RM0008 Secure digital input/output interface (SDIO) Bit 2 DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte data transfer. 0: Block data transfer 1: Stream or SDIO multibyte data transfer on STM32F10xxx XL-density devices. Stream data transfer on STM32F10xxx high-density devices. Bit 1 DTDIR: Data transfer direction selection 0: From controller to card.
Page 605: Sdio Status Register (Sdio_Sta)
Secure digital input/output interface (SDIO) RM0008 22.9.11 SDIO status register (SDIO_STA) Address offset: 0x34 Reset value: 0x0000 0000 The SDIO_STA register is a read-only register. It contains two types of flag: • Static flags (bits [23:22,10:0]): these bits remain asserted until they are cleared by writing to the SDIO Interrupt Clear register (see SDIO_ICR) •...
Page 606: Sdio Interrupt Clear Register (Sdio_Icr)
RM0008 Secure digital input/output interface (SDIO) Bit 4 TXUNDERR: Transmit FIFO underrun error Bit 3 DTIMEOUT: Data timeout Bit 2 CTIMEOUT: Command response timeout The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods. Bit 1 DCRCFAIL: Data block sent/received (CRC check failed) Bit 0 CCRCFAIL: Command response received (CRC check failed) 22.9.12 SDIO interrupt clear register (SDIO_ICR)
Page 607 Secure digital input/output interface (SDIO) RM0008 Bit 7 CMDSENTC: CMDSENT flag clear bit Set by software to clear the CMDSENT flag. 0: CMDSENT not cleared 1: CMDSENT cleared Bit 6 CMDRENDC: CMDREND flag clear bit Set by software to clear the CMDREND flag. 0: CMDREND not cleared 1: CMDREND cleared Bit 5 RXOVERRC: RXOVERR flag clear bit...
Page 608: Sdio Mask Register (Sdio_Mask)
RM0008 Secure digital input/output interface (SDIO) 22.9.13 SDIO mask register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24...
Page 609 Secure digital input/output interface (SDIO) RM0008 Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full.
Page 610: Sdio Fifo Counter Register (Sdio_Fifocnt)
RM0008 Secure digital input/output interface (SDIO) Bit 6 CMDRENDIE: Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response. 0: Command response received interrupt disabled 1: command Response Received interrupt enabled Bit 5 RXOVERRIE: Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error.
Page 611: Sdio Data Fifo Register (Sdio_Fifo)
Secure digital input/output interface (SDIO) RM0008 22.9.15 SDIO data FIFO register (SDIO_FIFO) Address offset: 0x80 Reset value: 0x0000 0000 The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
Page 612 RM0008 Secure digital input/output interface (SDIO) Table 168. SDIO register map (continued) Offset Register SDIO_D- Reserved DATACOUNT 0x30 COUNT 0x34 SDIO_STA 0x38 SDIO_ICR 0x3C SDIO_MASK SDIO_FIFO- Reserved FIFOCOUNT 0x48 FIF0Data 0x80 SDIO_FIFO Refer to Table 3 on page 51 for the register boundary addresses. DocID13902 Rev 15 612/1128...
Page 613: Universal Serial Bus Full-Speed Device Interface (Usb)
Universal serial bus full-speed device interface (USB) RM0008 Universal serial bus full-speed device interface (USB) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
Page 614: Figure 219. Usb Peripheral Block Diagram
RM0008 Universal serial bus full-speed device interface (USB) Figure 219. USB peripheral block diagram USB clock (48 MHz) Analog transceiver PCLK1 Control Clock RX-TX registers & logic recovery Suspend timer Control Endpoint Interrupt selection registers & logic S.I.E. Packet buffer Endpoint Endpoint interface...
Page 615: Description Of Usb Blocks
Universal serial bus full-speed device interface (USB) RM0008 Each endpoint is associated with a buffer description block indicating where the endpoint related memory area is located, how large it is or how many bytes must be transmitted. When a token for a valid function/endpoint pair is recognized by the USB peripheral, the related data transfer (if required and if the endpoint is configured) takes place.
Page 616: Programming Considerations
RM0008 Universal serial bus full-speed device interface (USB) endpoints* in any combination. For example the USB peripheral can be programmed to have 4 double buffer endpoints and 8 single-buffer/mono-directional endpoints. • Control Registers: These are the registers containing information about the status of the whole USB peripheral and used to force some USB events, such as resume and power-down.
Page 617: System And Power-On Reset
Universal serial bus full-speed device interface (USB) RM0008 23.4.2 System and power-on reset Upon system and power-on reset, the first operation the application software should perform is to provide all required clock signals to the USB peripheral and subsequently de-assert its reset signal so to be able to access its registers.
Page 618: Figure 220. Packet Buffer Areas With Examples Of Buffer Description Table Locations
RM0008 Universal serial bus full-speed device interface (USB) back-to-back accesses. The USB peripheral logic uses a dedicated clock. The frequency of this dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different from the clock used for the interface to the APB1 bus. Different clock configurations are possible where the APB1 clock frequency can be higher or lower than the USB peripheral one.
Page 619 Universal serial bus full-speed device interface (USB) RM0008 Each packet buffer is used either during reception or transmission starting from the bottom. The USB peripheral will never change the contents of memory locations adjacent to the allocated memory buffers; if a packet bigger than the allocated buffer length is received (buffer overrun condition) the data will be copied to the memory only up to the last available location.
Page 620 RM0008 Universal serial bus full-speed device interface (USB) indicating a flow control condition: the USB host will retry the transaction until it succeeds. It is mandatory to execute the sequence of operations in the above mentioned order to avoid losing the notification of a second IN transaction addressed to the same endpoint immediately following the one which triggered the CTR interrupt.
Page 621: Double-Buffered Endpoints
Universal serial bus full-speed device interface (USB) RM0008 processed. After the received data is processed, the application software should set the STAT_RX bits to ‘11 (Valid) in the USB_EPnR, enabling further transactions. While the STAT_RX bits are equal to ‘10 (NAK), any OUT request addressed to that endpoint is NAKed, indicating a flow control condition: the USB host will retry the transaction until it succeeds.
Page 622 RM0008 Universal serial bus full-speed device interface (USB) bulk endpoint type is the most suited model. This is because the host schedules bulk transactions so as to fill all the available bandwidth in the frame, maximizing the actual transfer rate as long as the USB function is ready to handle a bulk transaction addressed to it.
Page 623: Table 169. Double-Buffering Buffer Flag Definition
Universal serial bus full-speed device interface (USB) RM0008 Since the swapped buffer management requires the usage of all 4 buffer description table locations hosting the address pointer and the length of the allocated memory buffers, the USB_EPnR registers used to implement double-buffered bulk endpoints are forced to be used as unidirectional ones.
Page 624: Table 170. Bulk Double-Buffering Memory Buffers Usage
RM0008 Universal serial bus full-speed device interface (USB) Table 170. Bulk double-buffering memory buffers usage Endpoint Packet buffer used by USB Packet buffer used by DTOG SW_BUF Type Peripheral Application Software ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1 Buffer description table locations. Buffer description table locations.
Page 625: Isochronous Transfers
Universal serial bus full-speed device interface (USB) RM0008 The application software can always override the special flow control implemented for double-buffered bulk endpoints, writing an explicit status different from ‘11 (Valid) into the STAT bit pair of the related USB_EPnR register. In this case, the USB peripheral will always use the programmed endpoint status, regardless of the buffer usage condition.
Page 626: Suspend/Resume Events
RM0008 Universal serial bus full-speed device interface (USB) As it happens with double-buffered bulk endpoints, the USB_EPnR registers used to implement Isochronous endpoints are forced to be used as unidirectional ones. In case it is required to have Isochronous endpoints enabled both for reception and transmission, two USB_EPnR registers must be used.
Page 627: Table 172. Resume Event Detection
Universal serial bus full-speed device interface (USB) RM0008 When an USB event occurs while the device is in SUSPEND mode, the RESUME procedure must be invoked to restore nominal clocks and regain normal USB behavior. Particular care must be taken to insure that this process does not take more than 10mS when the wakening event is an USB reset sequence (See “Universal Serial Bus Specification”...
Page 628: Usb Registers
RM0008 Universal serial bus full-speed device interface (USB) 23.5 USB registers The USB peripheral registers can be divided into the following groups: • Common Registers: Interrupt and Control registers • Endpoint Registers: Endpoint configuration and status • Buffer Descriptor Table: Location of packet memory used to locate data buffers All register addresses are expressed as offsets with respect to the USB peripheral registers base address 0x4000 5C00, except the buffer descriptor table locations, which starts at the address specified by the USB_BTABLE register.
Page 629 Universal serial bus full-speed device interface (USB) RM0008 Bit 11 SUSPM: Suspend mode interrupt mask 0: Suspend Mode Request (SUSP) Interrupt disabled. 1: SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set. Bit 10 RESETM: USB reset interrupt mask 0: RESET Interrupt disabled.
Page 630 RM0008 Universal serial bus full-speed device interface (USB) USB interrupt status register (USB_ISTR) Address offset: 0x44 Reset value: 0x0000 0000 WKUP SUSP RESET ESOF EP_ID[3:0] Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 This register contains the status of all the interrupt sources allowing application software to determine, which events caused an interrupt request.
Page 631 Universal serial bus full-speed device interface (USB) RM0008 The following describes each bit in detail: Bit 15 CTR: Correct transfer This bit is set by the hardware to indicate that an endpoint has successfully completed a transaction; using DIR and EP_ID bits software can determine which endpoint requested the interrupt.
Page 632 RM0008 Universal serial bus full-speed device interface (USB) Bit 10 RESET: USB reset request Set when the USB peripheral detects an active USB RESET signal at its inputs. The USB peripheral, in response to a RESET, just resets its internal protocol state machine, generating an interrupt if RESETM enable bit in the USB_CNTR register is set.
Page 633 Universal serial bus full-speed device interface (USB) RM0008 USB frame number register (USB_FNR) Address offset: 0x48 Reset value: 0x0XXX where X is undefined RXDP RXDM LSOF[1:0] FN[10:0] Bit 15 RXDP: Receive data + line status This bit can be used to observe the status of received data plus upstream port data line. It can be used during end-of-suspend routines to help determining the wakeup event.
Page 634 RM0008 Universal serial bus full-speed device interface (USB) USB device address (USB_DADDR) Address offset: 0x4C Reset value: 0x0000 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Reserved Bits 15:8 Reserved Bit 7 EF: Enable function This bit is set by the software to enable the USB device. The address of this device is contained in the following ADD[6:0] bits.
Page 635: Endpoint-Specific Registers
Universal serial bus full-speed device interface (USB) RM0008 23.5.2 Endpoint-specific registers The number of these registers varies according to the number of endpoints that the USB peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional endpoints. Each USB device must support a control endpoint whose address (EA bits) must be set to 0.
Page 636 RM0008 Universal serial bus full-speed device interface (USB) Bit 15 CTR_RX: Correct Transfer for reception This bit is set by the hardware when an OUT/SETUP transaction is successfully completed on this endpoint; the software can only clear this bit. If the CTRM bit in USB_CNTR register is set accordingly, a generic interrupt condition is generated together with the endpoint related interrupt condition, which is always activated.
Page 637 Universal serial bus full-speed device interface (USB) RM0008 Bits 10:9 EP_TYPE[1:0]: Endpoint type These bits configure the behavior of this endpoint as described in Table 174: Endpoint type encoding on page 638. Endpoint 0 must always be a control endpoint and each USB function must have at least one control endpoint which has address 0, but there may be other control endpoints if required.
Page 638: Table 173. Reception Status Encoding
RM0008 Universal serial bus full-speed device interface (USB) Bit 6 DTOG_TX: Data Toggle, for transmission transfers If the endpoint is non-isochronous, this bit contains the required value of the data toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware toggles this bit when the ACK handshake is received from the USB host, following a data packet transmission.
Page 639: Table 175. Endpoint Kind Meaning
Universal serial bus full-speed device interface (USB) RM0008 Table 174. Endpoint type encoding (continued) EP_TYPE[1:0] Meaning INTERRUPT Table 175. Endpoint kind meaning EP_TYPE[1:0] EP_KIND Meaning BULK DBL_BUF CONTROL STATUS_OUT Not used INTERRUPT Not used Table 176. Transmission status encoding STAT_TX[1:0] Meaning DISABLED: all transmission requests addressed to this endpoint are ignored.
Page 640: Buffer Descriptor Table
RM0008 Universal serial bus full-speed device interface (USB) 23.5.3 Buffer descriptor table Although the buffer descriptor table is located inside the packet buffer memory, its entries can be considered as additional registers used to configure the location and size of the packet buffers used to exchange data between the USB macro cell and the STM32F10xxx.
Page 641 Universal serial bus full-speed device interface (USB) RM0008 Transmission byte count n (USB_COUNTn_TX) Address offset: [USB_BTABLE] + n*16 + 4 USB local Address: [USB_BTABLE] + n*8 + 2 COUNTn_TX[9:0] Reserved Bits 15:10 These bits are not used since packet size is limited by USB specifications to 1023 bytes. Their value is not considered by the USB peripheral.
Page 642 RM0008 Universal serial bus full-speed device interface (USB) Reception byte count n (USB_COUNTn_RX) Address offset: [USB_BTABLE] + n*16 + 12 USB local Address: [USB_BTABLE] + n*8 + 6 BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0] This table location is used to store two different values, both required during packet reception.
Page 643: Usb Register Map
Universal serial bus full-speed device interface (USB) RM0008 Table 177. Definition of allocated buffer memory Value of Memory allocated Memory allocated NUM_BLOCK[4:0] when BL_SIZE=0 when BL_SIZE=1 0 (‘00000) Not allowed 32 bytes 1 (‘00001) 2 bytes 64 bytes 2 (‘00010) 4 bytes 96 bytes 3 (‘00011)
Page 644 RM0008 Universal serial bus full-speed device interface (USB) Table 178. USB register map and reset values (continued) Offset Register STAT_ STAT_ USB_EP4R TYPE EA[3:0] 0x10 Reserved [1:0] [1:0] [1:0] Reset value STAT_ STAT_ USB_EP5R TYPE EA[3:0] 0x14 Reserved [1:0] [1:0] [1:0] Reset value STAT_...
Page 645: Controller Area Network (Bxcan)
Controller area network (bxCAN) RM0008 Controller area network (bxCAN) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 646: Bxcan General Description
RM0008 Controller area network (bxCAN) Time-triggered communication option • Disable automatic retransmission mode • 16-bit free running timer • Time Stamp sent in last two data bytes Management • Maskable interrupts • Software-efficient mailbox mapping at a unique address space Dual CAN (connectivity line only) •...
Page 647: Can 2.0B Active Core
Controller area network (bxCAN) RM0008 Figure 221. CAN network topology Application Controller Transceiver High CAN Bus 24.3.1 CAN 2.0B active core The bxCAN module handles the transmission and the reception of CAN messages fully autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully supported by hardware.
Page 648: Bxcan Operating Modes
RM0008 Controller area network (bxCAN) Figure 222. Dual CAN block diagram (connectivity devices) 24.4 bxCAN operating modes bxCAN has three main operating modes: initialization, normal and Sleep. After a hardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pull- up is active on CANTX.
Page 649: Initialization Mode
Controller area network (bxCAN) RM0008 mode. Before entering normal mode bxCAN always has to synchronize on the CAN bus. To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive recessive bits have been monitored on CANRX. 24.4.1 Initialization mode The software initialization can be done while the hardware is in Initialization mode.
Page 650: Test Mode
RM0008 Controller area network (bxCAN) bxCAN can be woken up (exit Sleep mode) either by software clearing the SLEEP bit or on detection of CAN bus activity. On CAN bus activity detection, hardware automatically performs the wakeup sequence by clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is cleared, software has to clear the SLEEP bit when a wakeup interrupt occurs, in order to exit from Sleep mode.
Page 651: Loop Back Mode
Controller area network (bxCAN) RM0008 remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames). Figure 224. bxCAN in silent mode bxCAN CANTX CANRX 24.5.2...
Page 652: Debug Mode
RM0008 Controller area network (bxCAN) Figure 226. bxCAN in combined mode bxCAN CANTX CANRX 24.6 Debug mode ® When the microcontroller enters the debug mode (Cortex -M3 core halted), the bxCAN continues to work normally or stops, depending on: • the DBG_CAN1_STOP bit for CAN1 or the DBG_CAN2_STOP bit for CAN2 in the DBG module.
Page 653: Figure 227. Transmit Mailbox States
Controller area network (bxCAN) RM0008 The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission. Abort A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR register.
Page 654: Time Triggered Communication Mode
RM0008 Controller area network (bxCAN) 24.7.2 Time triggered communication mode In this mode, the internal counter of the CAN hardware is activated and used to generate the Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to Section 24.7.7: Bit timing).
Page 655: Identifier Filtering
Controller area network (bxCAN) RM0008 FIFO management Starting from the empty state, the first valid message received is stored in the FIFO which becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CAN_RFR register to the value 01b. The message is available in the FIFO output mailbox. The software reads out the mailbox content and releases it by setting the RFOM bit in the CAN_RFR register.
Page 656 RM0008 Controller area network (bxCAN) otherwise needed to perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0 and CAN_FxR1. Scalable width To optimize and adapt the filters to the application needs, each filter bank can be scaled independently.
Page 657: Figure 229. Filter Bank Scale Configuration - Register Organization
Controller area network (bxCAN) RM0008 Figure 229. Filter bank scale configuration - register organization Filter Num. One 32-Bit Filter - Identifier Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] Mask CAN_FxR2[31:24] CAN_FxR2[23:16] CAN_FxR2[15:8] CAN_FxR2[7:0] Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] Two 32-Bit Filters - Identifier List CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8]...
Page 658: Figure 230. Example Of Filter Numbering
RM0008 Controller area network (bxCAN) Figure 230. Example of filter numbering Filter Filter Filter Filter FIFO0 FIFO1 Bank Num. Bank Num. ID List (32-bit) ID Mask (16-bit) ID Mask (32-bit) ID List (32-bit) Deactivated ID List (16-bit) ID Mask (16-bit) Deactivated ID Mask (16-bit) ID List (32-bit)
Page 659: Message Storage
Controller area network (bxCAN) RM0008 Figure 231. Filtering mechanism - example Example of 3 filter banks in 32-bit Unidentified List mode and the remaining in 32-bit Identifier Mask mode Message Received Identifier Data Ctrl Filter bank Receive FIFO Identifier Identifier Message Stored Identifier...
Page 660: Table 179. Transmit Mailbox Mapping
RM0008 Controller area network (bxCAN) Table 179. Transmit mailbox mapping Offset to transmit mailbox base address Register name CAN_TIxR CAN_TDTxR CAN_TDLxR CAN_TDHxR Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox.
Page 661: Error Management
Controller area network (bxCAN) RM0008 24.7.6 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error Counter (REC value, in the CAN_ESR register), which get incremented or decremented according to the error condition.
Page 662: Figure 233. Bit Timing
RM0008 Controller area network (bxCAN) A valid edge is defined as the first transition in a bit time from dominant to recessive bus level provided the controller itself does not send a recessive bit. If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so that the sample point is delayed.
Page 663: Bxcan Interrupts
Controller area network (bxCAN) RM0008 Figure 234. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Ctrl Field Data Field CRC Field Ack Field Arbitration Field 8 * N Inter-Frame Space Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame...
Page 664: Figure 235. Event Flags And Interrupt Generation
RM0008 Controller area network (bxCAN) Figure 235. Event flags and interrupt generation CAN_IER TRANSMIT INTERRUPT TMEIE RQCP0 & CAN_TSR RQCP1 RQCP2 FMPIE0 & FIFO 0 FMP0 INTERRUPT FFIE0 & CAN_RF0R FULL0 FOVIE0 & FOVR0 FMPIE1 & FIFO 1 FMP1 INTERRUPT FFIE1 &...
Page 665: Can Registers
Controller area network (bxCAN) RM0008 – Wakeup condition, SOF monitored on the CAN Rx signal. – Entry into Sleep mode. 24.9 CAN registers The peripheral registers have to be accessed by words (32 bits). 24.9.1 Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network.
Page 666 RM0008 Controller area network (bxCAN) Bit 7 TTCM: Time triggered communication mode 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode, please refer to Section 24.7.2: Time triggered communication mode.
Page 667 Controller area network (bxCAN) RM0008 Bit 0 INRQ Initialization request The software clears this bit to switch the hardware into normal mode. Once 11 consecutive recessive bits have been monitored on the Rx signal the CAN hardware is synchronized and ready for transmission and reception.
Page 668 RM0008 Controller area network (bxCAN) Bit 2 ERRI Error interrupt This bit is set by hardware when a bit of the CAN_ESR has been set on error detection and the corresponding interrupt in the CAN_IER is enabled. Setting this bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is set.
Page 669 Controller area network (bxCAN) RM0008 Bit 26 TME0 Transmit mailbox 0 empty This bit is set by hardware when no transmit request is pending for mailbox 0. Bits 25:24 CODE[1:0] Mailbox code In case at least one transmit mailbox is free, the code value is equal to the number of the next transmit mailbox free.
Page 670 RM0008 Controller area network (bxCAN) Bit 7 ABRQ0 Abort request for mailbox0 Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bits 6:4 Reserved, must be kept at reset value.
Page 671 Controller area network (bxCAN) RM0008 Bits 1:0 FMP0[1:0] FIFO 0 message pending These bits indicate how many messages are pending in the receive FIFO. FMP is increased each time the hardware stores a new message in to the FIFO. FMP is decreased each time the software releases the output mailbox by setting the RFOM0 bit.
Page 672 RM0008 Controller area network (bxCAN) Bits 31:18 Reserved, must be kept at reset value. Bit 17 SLKIE Sleep interrupt enable 0: No interrupt when SLAKI bit is set. 1: Interrupt generated when SLAKI bit is set. Bit 16 WKUIE Wakeup interrupt enable 0: No interrupt when WKUI is set.
Page 673 Controller area network (bxCAN) RM0008 Bit 2 FFIE0 FIFO full interrupt enable 0: No interrupt when FULL bit is set. 1: Interrupt generated when FULL bit is set. Bit 1 FMPIE0 FIFO message pending interrupt enable 0: No interrupt generated when state of FMP[1:0] bits are not 00b. 1: Interrupt generated when state of FMP[1:0] bits are not 00b.
Page 674 RM0008 Controller area network (bxCAN) Bit 2 BOFF Bus-off flag This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on TEC overflow, greater than 255, refer to Section 24.7.6 on page 661. Bit 1 EPVF: Error passive flag This bit is set by hardware when the Error Passive limit has been reached (Receive Error Counter or Transmit Error Counter>127).
Page 675: Can Mailbox Registers
Controller area network (bxCAN) RM0008 Bits 19:16 TS1[3:0] Time segment 1 These bits define the number of time quanta in Time Segment 1 x (TS1[3:0] + 1) For more information on bit timing, please refer to Section 24.7.7: Bit timing on page 661.
Page 676 RM0008 Controller area network (bxCAN) CAN TX mailbox identifier register (CAN_TIxR) (x=0..2) Address offsets: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (except bit 0, TXRQ = 0) All TX registers are write protected when the mailbox is pending transmission (TMEx reset). This register also implements the TX request control (bit 0) - reset value 0.
Page 677 Controller area network (bxCAN) RM0008 CAN mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX TIME[15:0] DLC[3:0] Reserved...
Page 678 RM0008 Controller area network (bxCAN) CAN mailbox data low register (CAN_TDLxR) (x=0..2) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x188, 0x198, 0x1A8 Reset value: 0xXXXX XXXX DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Bits 31:24 DATA3[7:0] Data byte 3...
Page 679 Controller area network (bxCAN) RM0008 CAN receive FIFO mailbox identifier register (CAN_RIxR) (x=0..1) Address offsets: 0x1B0, 0x1C0 Reset value: 0xXXXX XXXX All RX registers are write protected. STID[10:0]/EXID[28:18] EXID[17:13] EXID[12:0] Res. Bits 31:21 STID[10:0]/EXID[28:18] Standard identifier or extended identifier The standard identifier or the MSBs of the extended identifier (depending on the IDE bit value).
Page 680 RM0008 Controller area network (bxCAN) CAN receive FIFO mailbox data length control and time stamp register (CAN_RDTxR) (x=0..1) Address offsets: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX All RX registers are write protected. TIME[15:0] FMI[7:0] DLC[3:0] Reserved Bits 31:16 TIME[15:0] Message time stamp This field contains the 16-bit timer value captured at the SOF detection.
Page 681 Controller area network (bxCAN) RM0008 CAN receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1) All bits of this register are write protected when the mailbox is not in empty state. Address offsets: 0x1B8, 0x1C8 Reset value: 0xXXXX XXXX All RX registers are write protected. DATA3[7:0] DATA2[7:0] DATA1[7:0]...
Page 682: Can Filter Registers
RM0008 Controller area network (bxCAN) 24.9.4 CAN filter registers CAN filter master register (CAN_FMR) Address offset: 0x200 Reset value: 0x2A1C 0E01 All bits of this register are set and cleared by software. Reserved Bits 31:1 Reserved, must be kept at reset value. Bit 0 FINIT Filter init mode Initialization mode for filter banks...
Page 683 Controller area network (bxCAN) RM0008 CAN filter mode register (CAN_FM1R) Address offset: 0x204 Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register. FBM2 FBM2 FBM2 FBM2 FBM2 FBM2 FBM2 FBM2...
Page 684 RM0008 Controller area network (bxCAN) Note: Please refer to Figure 229: Filter bank scale configuration - register organization on page 657. CAN filter FIFO assignment register (CAN_FFA1R) Address offset: 0x214 Reset value: 0x0000 0000 This register can be written only when the filter initialization mode is set (FINIT=1) in the CAN_FMR register.
Page 685 Controller area network (bxCAN) RM0008 Filter bank i register x (CAN_FiRx) (i=0..27, x=1, 2) Address offsets: 0x240..0x31C Reset value: 0xXXXX XXXX n connectivity line devices there are 28 filter banks, i=0 .. 27, in other devices there are 14 filter banks i = 0 ..13. Each filter bank i is composed of two 32-bit registers, CAN_FiR[2:1]. This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared or when the FINIT bit of the CAN_FMR register is set.
Page 686: Bxcan Register Map
RM0008 Controller area network (bxCAN) 24.9.5 bxCAN register map Refer to Table 3 on page 51 for the register boundary addresses. In connectivity line devices, the registers from offset 0x200 to 31C are present only in CAN1. Table 181. bxCAN register map and reset values Offset Register CAN_MCR...
Page 687 Controller area network (bxCAN) RM0008 Table 181. bxCAN register map and reset values (continued) Offset Register CAN_TDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] 0x188 Reset value CAN_TDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x18C Reset value CAN_TI1R STID[10:0]/EXID[28:18] EXID[17:0] 0x190 Reset value CAN_TDT1R TIME[15:0] DLC[3:0] 0x194 Reserved...
Page 688 RM0008 Controller area network (bxCAN) Table 181. bxCAN register map and reset values (continued) Offset Register CAN_RDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0] 0x1BC Reset value CAN_RI1R STID[10:0]/EXID[28:18] EXID[17:0] 0x1C0 Reset value CAN_RDT1R TIME[15:0] FMI[7:0] DLC[3:0] 0x1C4 Reserved Reset value CAN_RDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]...
Page 689 Controller area network (bxCAN) RM0008 Table 181. bxCAN register map and reset values (continued) Offset Register CAN_F0R1 FB[31:0] 0x240 Reset value CAN_F0R2 FB[31:0] 0x244 Reset value CAN_F1R1 FB[31:0] 0x248 Reset value CAN_F1R2 FB[31:0] 0x24C Reset value CAN_F27R1 FB[31:0] 0x318 Reset value CAN_F27R2 FB[31:0] 0x31C...
Page 690: Serial Peripheral Interface (Spi)
RM0008 Serial peripheral interface (SPI) Serial peripheral interface (SPI) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 691: Spi And I 2 S Main Features
Serial peripheral interface (SPI) RM0008 25.2 SPI and I S main features 25.2.1 SPI features • Full-duplex synchronous transfers on three lines • Simplex synchronous transfers on two lines with or without a bidirectional data line • 8- or 16-bit transfer frame format selection •...
Page 692: I 2 S Features
RM0008 Serial peripheral interface (SPI) 25.2.2 S features • Half-duplex communication (only transmitter or receiver) • Master or slave operations • 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8 kHz to 192 kHz) • Data format may be 16-bit, 24-bit or 32-bit •...
Page 693: Spi Functional Description
Serial peripheral interface (SPI) RM0008 25.3 SPI functional description 25.3.1 General description The block diagram of the SPI is shown in Figure 237. Figure 237. SPI block diagram Usually, the SPI is connected to external devices through 4 pins: • MISO: Master In / Slave Out data.
Page 694: Figure 238. Single Master/ Single Slave Application
RM0008 Serial peripheral interface (SPI) enters the master mode fault state: the MSTR bit is automatically cleared and the device is configured in slave mode (refer to Section 25.3.10: Error flags on page 712). A basic example of interconnections between a single master and a single slave is illustrated in Figure 238.
Page 695 Serial peripheral interface (SPI) RM0008 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.
Page 696: Configuring The Spi In Slave Mode
RM0008 Serial peripheral interface (SPI) Figure 239. Data clock timing diagram 1. These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register. Data frame format Data can be shifted out either MSB-first or LSB-first depending on the value of the LSBFIRST bit in the SPI_CR1 Register.
Page 697 Serial peripheral interface (SPI) RM0008 Procedure Set the DFF bit to define 8- or 16-bit data frame format Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 239).
Page 698: Configuring The Spi In Master Mode
RM0008 Serial peripheral interface (SPI) 25.3.3 Configuring the SPI in master mode In the master configuration, the serial clock is generated on the SCK pin. Procedure Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register). Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure...
Page 699: Configuring The Spi For Half-Duplex Communication
Serial peripheral interface (SPI) RM0008 25.3.4 Configuring the SPI for half-duplex communication The SPI is capable of operating in half-duplex mode in 2 configurations. • 1 clock and 1 bidirectional data wire • 1 clock and 1 data wire (receive-only or transmit-only) 1 clock and 1 bidirectional data wire (BIDIMODE=1) This mode is enabled by setting the BIDIMODE bit in the SPI_CR1 register.
Page 700 RM0008 Serial peripheral interface (SPI) Start sequence in master mode • In full-duplex (BIDIMODE=0 and RXONLY=0) – The sequence begins when data are written into the SPI_DR register (Tx buffer). – The data are then parallel loaded from the Tx buffer into the 8-bit shift register during the first bit transmission and then shifted out serially to the MOSI pin.
Page 701 Serial peripheral interface (SPI) RM0008 software must have written the data to be sent before the SPI master device initiates the transfer. – No data are received. • In bidirectional mode, when receiving (BIDIMODE=1 and BIDIOE=0) – The sequence begins when the slave device receives the clock signal and the first bit of the data on its MISO pin.
Page 702: Figure 240. Txe/Rxne/Bsy Behavior In Master / Full-Duplex Mode (Bidimode=0 And Rxonly=0) In The Case Of Continuous Transfers
RM0008 Serial peripheral interface (SPI) Figure 240. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers Example in Master mode with CPOL=1, CPHA=1 DATA1 = 0xF1 DATA2 = 0xF2 DATA3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware...
Page 703: Figure 242. Txe/Bsy Behavior In Master Transmit-Only Mode (Bidimode=0 And Rxonly=0) In
Serial peripheral interface (SPI) RM0008 Transmit-only procedure (BIDIMODE=0 RXONLY=0) In this mode, the procedure can be reduced as described below and the BSY bit can be used to wait until the completion of the transmission (see Figure 242 Figure 243). Enable the SPI by setting the SPE bit to 1.
Page 704: Figure 243. Txe/Bsy In Slave Transmit-Only Mode (Bidimode=0 And Rxonly=0) In The Case Of
RM0008 Serial peripheral interface (SPI) Figure 243. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in the case of continuous transfers Example in slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware...
Page 705: Figure 244. Rxne Behavior In Receive-Only Mode (Bidirmode=0 And Rxonly=1) In The Case Of
Serial peripheral interface (SPI) RM0008 Figure 244. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in the case of continuous transfers Example with CPOL=1, CPHA=1, RXONLY=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware cleared by software...
Page 706: Crc Calculation
RM0008 Serial peripheral interface (SPI) Figure 245. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in the case of discontinuous transfers Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 TXE flag Tx buffer...
Page 707 Serial peripheral interface (SPI) RM0008 Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values. Program the polynomial in the SPI_CRCPR register. Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers. Enable the SPI by setting the SPE bit in the SPI_CR1 register.
Page 708: Status Flags
RM0008 Serial peripheral interface (SPI) 25.3.7 Status flags Four status flags are provided for the application to completely monitor the state of the SPI bus. Tx buffer empty flag (TXE) When it is set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can be loaded into the buffer.
Page 709: Disabling The Spi
Serial peripheral interface (SPI) RM0008 25.3.8 Disabling the SPI When a transfer is terminated, the application can stop the communication by disabling the SPI peripheral. This is done by clearing the SPE bit. For some configurations, disabling the SPI and entering the Halt mode while a transfer is ongoing can cause the current transfer to be corrupted and/or the BSY flag might become unreliable.
Page 710: Spi Communication Using Dma (Direct Memory Addressing)
RM0008 Serial peripheral interface (SPI) 25.3.9 SPI communication using DMA (direct memory addressing) To operate at its maximum speed, the SPI needs to be fed with the data for transmission and the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers, the SPI features a DMA capability implementing a simple request/acknowledge protocol.
Page 711: Figure 246. Transmission Using Dma
Serial peripheral interface (SPI) RM0008 Figure 246. Transmission using DMA Example with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hardware set by hardware cleared by DMA write...
Page 712: Error Flags
RM0008 Serial peripheral interface (SPI) DMA capability with CRC When SPI communication is enabled with CRC communication and DMA mode, the transmission and reception of the CRC at the end of communication are automatic that is without using the bit CRCNEXT. After the CRC reception, the CRC must be read in the SPI_DR register to clear the RXNE flag.
Page 713: Spi Interrupts
Serial peripheral interface (SPI) RM0008 CRC error This flag is used to verify the validity of the value received when the CRCEN bit in the SPI_CR1 register is set. The CRCERR flag in the SPI_SR register is set if the value received in the shift register does not match the receiver SPI_RXCRCR value.
Page 714: I 2 S Functional Description
RM0008 Serial peripheral interface (SPI) 25.4 S functional description The I S audio protocol is not available in low- and medium-density devices. This section concerns only high-density, XL-density and connectivity line devices. 25.4.1 S general description The block diagram of the I S is shown in Figure 248.
Page 715: Supported Audio Protocols
Serial peripheral interface (SPI) RM0008 The SPI could function as an audio I S interface when the I S capability is enabled (by setting the I2SMOD bit in the SPI_I2SCFGR register). This interface uses almost the same pins, flags and interrupts as the SPI. The I S shares three common pins with the SPI: •...
Page 716: Figure 249. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, Cpol = 0)
RM0008 Serial peripheral interface (SPI) The 24-bit and 32-bit data frames need two CPU read or write operations to/from the SPI_DR or two DMA operations if the DMA is preferred for the application. For 24-bit data frame specifically, the 8 nonsignificant bits are extended to 32 bits with 0-bits (by hardware). For all data formats and communication standards, the most significant bit is always sent first (MSB first).
Page 717: Figure 251. Transmitting 0X8Eaa33
Serial peripheral interface (SPI) RM0008 Figure 251. Transmitting 0x8EAA33 Second write to Data register First write to Data register 0x8EAA 0x33XX Only the 8 MSBs are sent to complete the 24 bits 8 LSB bits have no meaning and could be anything •...
Page 718: Figure 254. Example
RM0008 Serial peripheral interface (SPI) Figure 254. Example Only one access to SPI_DR 0X76A3 For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes place even if 0x0000 have not yet been sent because it is done by hardware.
Page 719: Figure 256. Msb Justified 24-Bit Frame Length With Cpol = 0
Serial peripheral interface (SPI) RM0008 Figure 256. MSB Justified 24-bit frame length with CPOL = 0 Reception Transmission 8-bit remaining 24-bit data 0 forced Channel left 32-bit Channel right Figure 257. MSB Justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit remaining...
Page 720: Figure 259. Lsb Justified 24-Bit Frame Length With Cpol = 0
RM0008 Serial peripheral interface (SPI) Figure 259. LSB Justified 24-bit frame length with CPOL = 0 Reception Transmission 24-bit remaining 8-bit data 0 forced Channel left 32-bit Channel right • In transmission mode: If data 0x3478AE have to be transmitted, two write operations to the SPI_DR register are required from software or by DMA.
Page 721: Figure 262. Lsb Justified 16-Bit Extended To 32-Bit Packet Frame With Cpol = 0
Serial peripheral interface (SPI) RM0008 Figure 262. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 Transmission Reception 16-bit remaining 16-bit data 0 forced Channel left 32-bit Channel right When 16-bit data frame extended to 32-bit channel frame is selected during the I configuration phase, Only one access to SPI_DR is required.
Page 722: Clock Generator
RM0008 Serial peripheral interface (SPI) Figure 264. PCM standard waveforms (16-bit) short frame fixed to 13-bit long frame 16-bit LSB MSB For long frame synchronization, the WS signal assertion time is fixed 13 bits in master mode. For short frame synchronization, the WS synchronization signal is only one cycle long. Figure 265.
Page 723: Figure 266. Audio Sampling Frequency Definition
Serial peripheral interface (SPI) RM0008 It will be: I S bitrate = 32 x 2 x F if the packet length is 32-bit wide. Figure 266. Audio sampling frequency definition 16-bit or 32-bit Left channel 16-bit or 32-bit Right channel 32-bits or 64-bits sampling point sampling point...
Page 724: Table 183. Audio-Frequency Precision Using Standard 8 Mhz Hse
RM0008 Serial peripheral interface (SPI) Table 183, Table 184 Table 185 provide example precision values for different clock configurations. Note: Other configurations are possible that allow optimum clock precision. Table 183. Audio-frequency precision using standard 8 MHz HSE (high-density and XL-density devices only) I2S_DIV I2S_ODD...
Page 725: Table 184. Audio-Frequency Precision Using Standard 25 Mhz And Pll3
Serial peripheral interface (SPI) RM0008 Table 184. Audio-frequency precision using standard 25 MHz and PLL3 (connectivity line devices only) Data Target Real fs PREDIV2 PLL3MUL I2SDIV I2SODD MCLK Error length fs(Hz) (KHz) 96000 95942.9825 0.0594% 48000 47971.4912 0.0594% 48000 47971.4912 0.0594% 44100 44102.823 0.0064%...
Page 726: Table 185. Audio-Frequency Precision Using Standard 14.7456 Mhz And Pll3
RM0008 Serial peripheral interface (SPI) Table 185. Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line devices only) Data Target Real fs PREDIV2 PLL3MUL I2SDIV I2SODD MCLK Error length fs(Hz) (KHz) 96000 96000 0.0000% 96000 96000 0.0000% 48000 48000 0.0000% 48000 48000...
Page 727: I 2 S Master Mode
Serial peripheral interface (SPI) RM0008 25.4.4 S master mode The I S can be configured in master mode for transmission and reception. This means that the serial clock is generated on the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not, thanks to the MCKOE bit in the SPI_I2SPR register.
Page 728: I 2 S Slave Mode
RM0008 Serial peripheral interface (SPI) Reception sequence The operating mode is the same as for the transmission mode except for the point 3 (refer to the procedure described in Section 25.4.4: I2S master mode), where the configuration should set the master reception mode through the I2SCFG[1:0] bits. Whatever the data or channel length, the audio data are received by 16-bit packets.
Page 729 Serial peripheral interface (SPI) RM0008 signals are input from the external master connected to the I S interface. There is then no need, for the user, to configure the clock. The configuration steps to follow are listed below: Set the I2SMOD bit in the SPI_I2SCFGR register to reach the I S functionalities and choose the I S standard through the I2SSTD[1:0] bits, the data length through the...
Page 730: Status Flags
RM0008 Serial peripheral interface (SPI) Reception sequence The operating mode is the same as for the transmission mode except for the point 1 (refer to the procedure described in Section 25.4.5: I2S slave mode), where the configuration should set the master reception mode using the I2SCFG[1:0] bits in the SPI_I2SCFGR register. Whatever the data length or the channel length, the audio data are received by 16-bit packets.
Page 731: Error Flags
Serial peripheral interface (SPI) RM0008 Tx buffer empty flag (TXE) When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to be transmitted.
Page 732: I 2 S Interrupts
RM0008 Serial peripheral interface (SPI) 25.4.8 S interrupts Table 186 provides the list of I S interrupts. Table 186. I S interrupt requests Interrupt event Event flag Enable Control bit Transmit buffer empty flag TXEIE Receive buffer not empty flag RXNE RXNEIE Overrun error...
Page 733: Spi And I 2 S Registers
Serial peripheral interface (SPI) RM0008 25.5 SPI and I S registers Refer to Section 2.1 on page 47 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits). 25.5.1 SPI control register 1 (SPI_CR1) (not used in I S mode)
Page 734 RM0008 Serial peripheral interface (SPI) Bit 10 RXONLY: Receive only This bit combined with the BIDImode bit selects the direction of transfer in 2-line unidirectional mode. This bit is also useful in a multislave system in which this particular slave is not accessed, the output from the accessed slave is not corrupted. 0: Full duplex (Transmit and receive) 1: Output disabled (Receive-only mode) Note: This bit is not used in I...
Page 735: Spi Control Register 2 (Spi_Cr2)
Serial peripheral interface (SPI) RM0008 Bit 2 MSTR: Master selection 0: Slave configuration 1: Master configuration Note: This bit should not be changed when communication is ongoing. It is not used in I S mode. Bit1 CPOL: Clock polarity 0: CK to 0 when idle 1: CK to 1 when idle Note: This bit should not be changed when communication is ongoing.
Page 736: Spi Status Register (Spi_Sr)
RM0008 Serial peripheral interface (SPI) Note: This bit is not used in I S mode Bit 1 TXDMAEN: Tx buffer DMA enable When this bit is set, the DMA request is made whenever the TXE flag is set. 0: Tx buffer DMA disabled 1: Tx buffer DMA enabled Bit 0 RXDMAEN: Rx buffer DMA enable When this bit is set, the DMA request is made whenever the RXNE flag is set.
Page 737: Spi Data Register (Spi_Dr)
Serial peripheral interface (SPI) RM0008 Bit 3 UDR: Underrun flag 0: No underrun occurred 1: Underrun occurred This flag is set by hardware and reset by a software sequence. Refer to Section 25.4.7 on page 731 for the software sequence. Note: This bit is not used in SPI mode.
Page 738: Spi Crc Polynomial Register (Spi_Crcpr) (Not Used In I
RM0008 Serial peripheral interface (SPI) 25.5.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I mode) Address offset: 0x10 Reset value: 0x0007 CRCPOLY[15:0] Bits 15:0 CRCPOLY[15:0]: CRC polynomial register This register contains the polynomial for the CRC calculation. The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be configured as required.
Page 739: Spi_I S Configuration Register (Spi_I2Scfgr)
Serial peripheral interface (SPI) RM0008 Bits 15:0 TXCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.
Page 740: Spi_I 2 S Prescaler Register (Spi_I2Spr)
RM0008 Serial peripheral interface (SPI) Bits 5:4 I2SSTD: I2S standard selection 00: I S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I S standards, refer to Section 25.4.2 on page 715.
Page 741 Serial peripheral interface (SPI) RM0008 Bits 15:10 Reserved, must be kept at reset value. Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I S is disabled.
Page 742: Spi Register Map
RM0008 Serial peripheral interface (SPI) 25.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 187. SPI register map and reset values Offset Register SPI_CR1 BR [2:0] 0x00 Reserved Reset value SPI_CR2 0x04 Reserved Reset value SPI_SR 0x08...
Page 743: Inter-Integrated Circuit (I 2 C) Interface
Inter-integrated circuit (I C) interface RM0008 Inter-integrated circuit (I C) interface Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 744: I 2 C Main Features
RM0008 Inter-integrated circuit (I C) interface 26.2 C main features • Parallel-bus/I C protocol converter • Multimaster capability: the same interface can act as Master or Slave • C Master features: – Clock generation – Start and Stop generation • C Slave features: –...
Page 745: C Functional Description
Inter-integrated circuit (I C) interface RM0008 26.3 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I C bus by a data pin (SDA) and by a clock pin (SCL).
Page 746: I2C Slave Mode
RM0008 Inter-integrated circuit (I C) interface Figure 269. I C block diagram Data register Data Data shift register control PEC calculation Comparator Own address register Dual address register Clock PEC register control Clock control Register (CCR) Control registers (CR1&CR2) Control Status registers logic (SR1&SR2)
Page 747 Inter-integrated circuit (I C) interface RM0008 Header or address not matched: the interface ignores it and waits for another Start condition. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set and waits for the 8-bit slave address. Address matched: the interface generates in sequence: •...
Page 748: Figure 270. Transfer Sequence Diagram For Slave Transmitter
RM0008 Inter-integrated circuit (I C) interface Figure 270. Transfer sequence diagram for slave transmitter 7-bit slave transmitter S Address Data1 Data2 DataN NA P ..EV1 EV3-1 EV3 EV3-2 10-bit slave transmitter S Header Address Header A Data1 ..DataN NA P EV1 EV3_1 EV3-2...
Page 749: I2C Master Mode
Inter-integrated circuit (I C) interface RM0008 Figure 271. Transfer sequence diagram for slave receiver 7-bit slave receiver S Address Data1 Data2 DataN ..10-bit slav e receiver S Header Address Data1 DataN ..Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN=1) EV1: ADDR=1, cleared by reading SR1 followed by reading SR2 EV2: RxNE=1 cleared by reading DR register.
Page 750 RM0008 Inter-integrated circuit (I C) interface SCL master clock generation The CCR bits are used to generate the high and low level of the SCL clock, starting from the generation of the rising and falling edge (respectively). As a slave may stretch the SCL line, the peripheral checks the SCL input from the bus at the end of the time programmed in TRISE bits after rising edge generation.
Page 751 Inter-integrated circuit (I C) interface RM0008 The master can decide to enter Transmitter or Receiver mode depending on the LSB of the slave address sent. • In 7-bit addressing mode, – To enter Transmitter mode, a master sends the slave address with LSB reset. –...
Page 752: Figure 272. Transfer Sequence Diagram For Master Transmitter
RM0008 Inter-integrated circuit (I C) interface Figure 272. Transfer sequence diagram for master transmitter 7-bit master transmitter Address Data1 Data2 DataN ..EV6 EV8_1 EV8_2 10-bit master transmitter Header Address Data1 DataN ..EV8_1 EV8_2 Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, EVx= Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
Page 753 Inter-integrated circuit (I C) interface RM0008 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: An acknowledge pulse if the ACK bit is set The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are...
Page 754: Figure 273. Method 1: Transfer Sequence Diagram For Master Receiver
RM0008 Inter-integrated circuit (I C) interface Figure 273. Method 1: transfer sequence diagram for master receiver 1. If a single byte is received, it is NA. 2. The EV5, EV6 and EV9 events stretch SCL low until the end of the corresponding software sequence. 3.
Page 755: Figure 274. Method 2: Transfer Sequence Diagram For Master Receiver When N>2
Inter-integrated circuit (I C) interface RM0008 Figure 274. Method 2: transfer sequence diagram for master receiver when N>2 7- bit master receiver Address Data1 Data2 DataN-2 DataN-1 DataN EV7_2 10- bit master receiver Header Address Header Data1 Data2 DataN-2 DataN-1 DataN EV7_2 Legend: S = Start, S...
Page 756: Figure 275. Method 2: Transfer Sequence Diagram For Master Receiver When N=2
RM0008 Inter-integrated circuit (I C) interface The procedure described above is valid for N>2. The cases where a single byte or two bytes are to be received should be handled differently, as described below: • Case of a single byte to be received: –...
Page 757: Error Conditions
Inter-integrated circuit (I C) interface RM0008 Figure 276. Method 2: transfer sequence diagram for master receiver when N=1 7- bit master receiver Address Data1 EV6_3 10- bit master receiver Header Address Header Data1 EV6_3 Legend: S = Start, S = Repeated Start, P = Stop, A = Acknowledge, NA = Non-acknowledge, EVx = Event (with interrupt if ITEVFEN = 1) EV5: SB=1, cleared by reading SR1 register followed by writing the DR register.
Page 758: Sda/Scl Line Control
RM0008 Inter-integrated circuit (I C) interface Arbitration lost (ARLO) This error occurs when the I C interface detects an arbitration lost condition. In this case, • the ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is set) •...
Page 759: Smbus
Inter-integrated circuit (I C) interface RM0008 26.3.6 SMBus Introduction The System Management Bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on I principles of operation. SMBus provides a control bus for system and power management related tasks.
Page 760 RM0008 Inter-integrated circuit (I C) interface Bus protocols The SMBus specification supports up to 9 bus protocols. For more details of these protocols and SMBus address types, refer to SMBus specification version. 2.0 (http://smbus.org/). These protocols should be implemented by the user software. Address resolution protocol (ARP) SMBus slave address conflicts can be resolved by dynamically assigning a new unique address to each slave device.
Page 761: Dma Requests
Inter-integrated circuit (I C) interface RM0008 Timeout error There are differences in the timing specifications between I C and SMBus. SMBus defines a clock low timeout, TIMEOUT of 35 ms. Also SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device.
Page 762 RM0008 Inter-integrated circuit (I C) interface Set the I2C_DR register address in the DMA_SxPAR register. The data will be moved to this address from the memory after each TxE event. Set the memory address in the DMA_SxMA0R register (and in DMA_SxMA1R register in the case of a bouble buffer mode).
Page 763: Packet Error Checking
Inter-integrated circuit (I C) interface RM0008 26.3.8 Packet error checking A PEC calculator has been implemented to improve the reliability of communication. The PEC is calculated by using the C(x) = x + x + 1 CRC-8 polynomial serially on each bit. •...
Page 764: Figure 277. I2C Interrupt Mapping Diagram
RM0008 Inter-integrated circuit (I C) interface Table 189. I C Interrupt requests (continued) Interrupt event Event flag Enable control bit Bus error BERR Arbitration loss (Master) ARLO Acknowledge failure Overrun/Underrun ITERREN PEC error PECERR Timeout/Tlow error TIMEOUT SMBus Alert SMBALERT Note: SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt channel.
Page 765: I 2 C Debug Mode
Inter-integrated circuit (I C) interface RM0008 26.5 C debug mode ® When the microcontroller enters the debug mode (Cortex -M3 core halted), the SMBUS timeout either continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT configuration bits in the DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C on page...
Page 766 RM0008 Inter-integrated circuit (I C) interface Bit 11 POS: Acknowledge/PEC Position (for data reception) This bit is set and cleared by software and cleared by hardware when PE=0. 0: ACK bit controls the (N)ACK of the current byte being received in the shift register. The PEC bit indicates that current byte in shift register is a PEC.
Page 767: I 2 C Control Register 2 (I2C_Cr2)
Inter-integrated circuit (I C) interface RM0008 Bit 3 SMBTYPE: SMBus type 0: SMBus Device 1: SMBus Host Bit 2 Reserved, must be kept at reset value Bit 1 SMBUS: SMBus mode 0: I C mode 1: SMBus mode Bit 0 PE: Peripheral enable 0: Peripheral disable 1: Peripheral enable Note: If this bit is reset while a communication is on going, the peripheral is disabled at the...
Page 768 RM0008 Inter-integrated circuit (I C) interface Bit 9 ITEVTEN: Event interrupt enable 0: Event interrupt disabled 1: Event interrupt enabled This interrupt is generated when: – SB = 1 (Master) – ADDR = 1 (Master/Slave) – ADD10= 1 (Master) – STOPF = 1 (Slave) –...
Page 769: I 2 C Own Address Register 1 (I2C_Oar1)
Inter-integrated circuit (I C) interface RM0008 26.6.3 C Own address register 1 (I2C_OAR1) Address offset: 0x08 Reset value: 0x0000 ADD[9:8] ADD[7:1] ADD0 MODE Reserved Bit 15 ADDMODE Addressing mode (slave mode) 0: 7-bit slave address (10-bit address not acknowledged) 1: 10-bit slave address (7-bit address not acknowledged) Bit 14 Should always be kept at 1 by software.
Page 770: C Data Register (I2C_Dr)
RM0008 Inter-integrated circuit (I C) interface 26.6.5 C Data register (I2C_DR) Address offset: 0x10 Reset value: 0x0000 DR[7:0] Reserved Bits 15:8 Reserved, must be kept at reset value Bits 7:0 DR[7:0] 8-bit data register Byte received or to be transmitted to the bus. –...
Page 771 Inter-integrated circuit (I C) interface RM0008 Bit 15 SMBALERT: SMBus alert In SMBus host mode: 0: no SMBALERT 1: SMBALERT event occurred on pin In SMBus slave mode: 0: no SMBALERT response address header 1: SMBALERT response address header to SMBALERT LOW received –...
Page 772 RM0008 Inter-integrated circuit (I C) interface Bit 9 ARLO: Arbitration lost (master mode) 0: No Arbitration Lost detected 1: Arbitration Lost detected Set by hardware when the interface loses the arbitration of the bus to another master – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).
Page 773 Inter-integrated circuit (I C) interface RM0008 Bit 3 ADD10: 10-bit header sent (Master mode) 0: No ADD10 event occurred. 1: Master has sent first address byte (header). – Set by hardware when the master has sent the first byte in 10-bit address mode. –...
Page 774: I 2 C Status Register 2 (I2C_Sr2)
RM0008 Inter-integrated circuit (I C) interface 26.6.7 C Status register 2 (I2C_SR2) Address offset: 0x18 Reset value: 0x0000 Note: Reading I2C_SR2 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR2 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared.
Page 775: I 2 C Clock Control Register (I2C_Ccr)
Inter-integrated circuit (I C) interface RM0008 Bit 2 TRA: Transmitter/receiver 0: Data bytes received 1: Data bytes transmitted This bit is set depending on the R/W bit of the address byte, at the end of total address phase. It is also cleared by hardware after detection of Stop condition (STOPF=1), repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.
Page 776: C Trise Register (I2C_Trise)
RM0008 Inter-integrated circuit (I C) interface Bit 14 DUTY: Fm mode duty cycle 0: Fm mode t high 1: Fm mode t = 16/9 (see CCR) high Bits 13:12 Reserved, must be kept at reset value Bits 11:0 CCR[11:0]: Clock control register in Fm/Sm mode (Master mode) Controls the SCL clock in master mode.
Page 777: I2C Register Map
Inter-integrated circuit (I C) interface RM0008 26.6.10 C register map The table below provides the I C register map and reset values. Table 190. I C register map and reset values Offset Register I2C_CR1 0x00 Reserved Reset value I2C_CR2 FREQ[5:0] 0x04 Reserved Reset value...
Page 778: Universal Synchronous Asynchronous Receiver Transmitter (Usart)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Universal synchronous asynchronous receiver transmitter (USART) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 779: Usart Main Features
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.2 USART main features • Full duplex, asynchronous communications • NRZ standard format (Mark/Space) • Fractional baud rate generator systems – A common programmable transmit and receive baud rates up to 4.5 MBits/s •...
Page 780: Usart Functional Description
RM0008 Universal synchronous asynchronous receiver transmitter (USART) • Transfer detection flags: – Receive buffer full – Transmit buffer empty – End of Transmission flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Four error detection flags: –...
Page 781 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Through these pins, serial data is transmitted and received in normal USART mode as frames comprising: • An Idle Line prior to transmission or reception • A start bit • A data word (8 or 9 bits) least significant bit first •...
Page 782: Figure 278. Usart Block Diagram
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 278. USART block diagram PWDATA PRDATA Write Read (DATA REGISTER) DR (CPU or DMA) (CPU or DMA) Receive Data Register (RDR) Transmit Data Register (TDR) IrDA ENDEC Receive Shift Register Transmit Shift Register BLOCK SW_RX GTPR...
Page 783: Usart Character Description
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.3.1 USART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the USART_CR1 register (see Figure 279). The TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data (The number of “1”...
Page 784: Transmitter
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the CK pin.
Page 785: Figure 280. Configurable Stop Bits
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 280. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible...
Page 786: Figure 281. Tc/Txe Behavior When Transmitting
RM0008 Universal synchronous asynchronous receiver transmitter (USART) When a transmission is taking place, a write instruction to the USART_DR register stores the data in the TDR register and which is copied in the shift register at the end of the current transmission.
Page 787: Receiver
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.3.3 Receiver The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register. Start bit detection In the USART, the start bit is detected when a specific sequence of samples is recognized. This sequence is: 1 1 1 0 X 0 X 0 X 0 0 0 0.
Page 788 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Character reception During a USART reception, data shifts in least significant bit first through the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the received shift register.
Page 789: Figure 283. Data Sampling For Noise Detection
Universal synchronous asynchronous receiver transmitter (USART) RM0008 The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs: •...
Page 790: Table 191. Noise Detection From Sampled Data
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Table 191. Noise detection from sampled data Sampled value NE status Received bit value Data validity Valid Not Valid Not Valid Not Valid Not Valid Not Valid Not Valid Valid When noise is detected in a frame: •...
Page 791: Fractional Baud Rate Generation
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Configurable stop bits during reception The number of stop bits to be received can be configured through the control bits of Control Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode. 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit.
Page 792: Table 192. Error Calculation For Programmed Baud Rates
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Example 2: To program USARTDIV = 0d25.62 This leads to: DIV_Fraction = 16*0d0.62 = 0d9.92 The nearest real number is 0d10 = 0xA DIV_Mantissa = mantissa (0d25.620) = 0d25 = 0x19 Then, USART_BRR = 0x19A hence USARTDIV = 0d25.625 Example 3: To program USARTDIV = 0d50.99 This leads to:...
Page 793: Usart Receiver's Tolerance To Clock Deviation
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.3.5 USART receiver’s tolerance to clock deviation The USART’s asynchronous receiver works correctly only if the total clock system deviation is smaller than the USART receiver’s tolerance. The causes which contribute to the total deviation are: •...
Page 794: Figure 284. Mute Mode Using Idle Line Detection
RM0008 Universal synchronous asynchronous receiver transmitter (USART) The non addressed devices may be placed in mute mode by means of the muting function. In mute mode: • None of the reception status bits can be set. • All the receive interrupts are inhibited. •...
Page 795: Parity Control
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 285. Mute mode using address mark detection In this example, the current address of the receiver is 1 RXNE RXNE RXNE (programmed in the USART_CR2 register) IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4...
Page 796: Lin (Local Interconnection Network) Mode
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.8 LIN (local interconnection network) mode The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode, the following bits must be kept cleared: • CLKEN in the USART_CR2 register, •...
Page 797: Figure 286. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 286. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBD is not set Break frame RX line Capture Strobe Break State machine Idle...
Page 798: Usart Synchronous Mode
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 287. Break detection in LIN mode vs. Framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK...
Page 799: Figure 288. Usart Example Of Synchronous Transmission
Universal synchronous asynchronous receiver transmitter (USART) RM0008 has been written). This means that it is not possible to receive a synchronous data without transmitting data. The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly.
Page 800: Single-Wire Half-Duplex Communication
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 290. USART data clock timing diagram (M=1) Idle or preceding Start transmission M=1 (9 data bits) Idle or next Stop transmission Clock (CPOL=0, CPHA=0) Clock (CPOL=0, CPHA=1) Clock (CPOL=1, CPHA=0) Clock (CPOL=1, CPHA=1) Data on TX (from master) MSB Stop...
Page 801: Smartcard
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Apart from this, the communications are similar to what is done in normal USART mode. The conflicts on the line must be managed by the software (by the use of a centralized arbiter, for instance). In particular, the transmission is never blocked by hardware and continue to occur as soon as a data is written in the data register while the TE bit is set.
Page 802 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Smartcard is a single wire half duplex communication protocol. • Transmission of data from the transmit shift register is guaranteed to be delayed by a minimum of 1/2 baud clock. In normal operation a full transmit shift register will start shifting on the next baud clock edge.
Page 803: Irda Sir Endec Block
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 293. Parity error detection using the 1.5 stop bits Bit 7 Parity Bit 1.5 Stop Bit 1 bit time 1.5 bit time sampling at sampling at 16th, 17th, 18th 8th, 9th, 10th 0.5 bit time 1 bit time sampling at...
Page 804 RM0008 Universal synchronous asynchronous receiver transmitter (USART) • IrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USARTsends data to the IrDA encoder), any data on the IrDA receive line is ignored by the IrDA decoder and if the Receiver is busy (USART receives decoded data from the USART), data on the TX from the USART to IrDA is not encoded by IrDA.
Page 805: Continuous Communication Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 294. IrDA SIR ENDEC- block diagram USART_TX Transmit IrDA_OUT SIREN Encoder USART IrDA_IN Receive Decoder USART_RX Figure 295. IrDA data modulation (3/16) -normal mode stop bit Start bit period IrDA_OUT 3/16 IrDA_IN 27.3.13 Continuous communication using DMA The USART is capable of continuing communication using the DMA.
Page 806: Figure 296. Transmission Using Dma
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Write the USART_DR register address in the DMA control register to configure it as the destination of the transfer. The data will be moved to this address from memory after each TXE event. Write the memory address in the DMA control register to configure it as the source of the transfer.
Page 807: Figure 297. Reception Using Dma
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Reception using DMA DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register. Data is loaded from the USART_DR register to a SRAM area configured using the DMA peripheral (refer to the DMA specification) whenever a data byte is received.
Page 808: Hardware Flow Control
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.3.14 Hardware flow control It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output. Figure 298 shows how to connect 2 devices in this mode: Figure 298.
Page 809: Usart Interrupts
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Figure 300. CTS flow control nCTS Transmit data register Data 2 empty Data 3 empty Stop Start Stop Idle Start Data 1 Data 2 Data 3 Writing data 3 in TDR Transmission of Data 3 is delayed until nCTS = 0 27.4 USART interrupts...
Page 810: Usart Mode Configuration
RM0008 Universal synchronous asynchronous receiver transmitter (USART) Figure 301. USART interrupt mapping diagram TCIE TXEIE CTSIE USART IDLE interrupt IDLEIE RXNEIE RXNEIE RXNE PEIE LBDIE DMAR 27.5 USART mode configuration Table 199. USART mode configuration USART modes USART1 USART2 USART3 UART4 UART5 Asynchronous mode...
Page 811: Status Register (Usart_Sr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.6.1 Status register (USART_SR) Address offset: 0x00 Reset value: 0x00C0 Reserved RXNE IDLE Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bits 31:10 Reserved, forced by hardware to 0. Bit 9 CTS: CTS flag This bit is set by hardware when the CTS input toggles, if the CTSE bit is set.
Page 812 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 4 IDLE: IDLE line detected This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the IDLEIE=1 in the USART_CR1 register. It is cleared by a software sequence (an read to the USART_SR register followed by a read to the USART_DR register).
Page 813: Data Register (Usart_Dr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.6.2 Data register (USART_DR) Address offset: 0x04 Reset value: Undefined Reserved DR[8:0] Reserved Bits 31:9 Reserved, forced by hardware to 0. Bits 8:0 DR[8:0]: Data value Contains the Received or Transmitted data character, depending on whether it is read from or written to.
Page 814: Control Register 1 (Usart_Cr1)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.6.4 Control register 1 (USART_CR1) Address offset: 0x0C Reset value: 0x0000 Reserved WAKE PEIE TXEIE TCIE RXNEIE IDLEIE Reserved Bits 31:14 Reserved, forced by hardware to 0. Bit 13 UE: USART enable When this bit is cleared the USART prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.
Page 815 Universal synchronous asynchronous receiver transmitter (USART) RM0008 Bit 6 TCIE: Transmission complete interrupt enable This bit is set and cleared by software. 0: Interrupt is inhibited 1: A USART interrupt is generated whenever TC=1 in the USART_SR register Bit 5 RXNEIE: RXNE interrupt enable This bit is set and cleared by software.
Page 816: Control Register 2 (Usart_Cr2)
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.6.5 Control register 2 (USART_CR2) Address offset: 0x10 Reset value: 0x0000 Reserved LINEN STOP[1:0] CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0] Res. Bits 31:15 Reserved, forced by hardware to 0. Bit 14 LINEN: LIN mode enable This bit is set and cleared by software.
Page 817: Control Register 3 (Usart_Cr3)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 Bit 8 LBCL: Last bit clock pulse This bit allows the user to select whether the clock pulse associated with the last data bit transmitted (MSB) has to be output on the CK pin in synchronous mode. 0: The clock pulse of the last data bit is not output to the CK pin 1: The clock pulse of the last data bit is output to the CK pin The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected...
Page 818 RM0008 Universal synchronous asynchronous receiver transmitter (USART) Bit 8 RTSE: RTS enable 0: RTS hardware flow control disabled 1: RTS interrupt enabled, data is only requested when there is space in the receive buffer. The transmission of data is expected to cease after the current character has been transmitted.
Page 819: Guard Time And Prescaler Register (Usart_Gtpr)
Universal synchronous asynchronous receiver transmitter (USART) RM0008 27.6.7 Guard time and prescaler register (USART_GTPR) Address offset: 0x18 Reset value: 0x0000 Reserved GT[7:0] PSC[7:0] Bits 31:16 Reserved, forced by hardware to 0. Bits 15:8 GT[7:0]: Guard time value This bit-field gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode.
Page 820: Usart Register Map
RM0008 Universal synchronous asynchronous receiver transmitter (USART) 27.6.8 USART register map The table below gives the USART register map and reset values. Table 200. USART register map and reset values Offset Register USART_SR 0x00 Reserved Reset value USART_DR DR[8:0] 0x04 Reserved Reset value DIV_Fraction...
Page 821: Usb On-The-Go Full-Speed (Otg_Fs)
USB on-the-go full-speed (OTG_FS) RM0008 USB on-the-go full-speed (OTG_FS) Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. High-density devices are STM32F101xx and STM32F103xx microcontrollers where the Flash memory density ranges between 256 and 512 Kbytes.
Page 822: Otg_Fs Main Features
RM0008 USB on-the-go full-speed (OTG_FS) 28.2 OTG_FS main features The main features can be divided into three categories: general, host-mode and device- mode features. 28.2.1 General features The OTG_FS interface general features are the following: • It is USB-IF certified to the Universal Serial Bus Specification Rev 2.0 •...
Page 823: Host-Mode Features
USB on-the-go full-speed (OTG_FS) RM0008 28.2.2 Host-mode features The OTG_FS interface main features and requirements in host-mode are the following: • External charge pump for V voltage generation. • Up to 8 host channels (pipes): each channel is dynamically reconfigurable to allocate any type of USB transfer.
Page 824: Otg_Fs Functional Description
RM0008 USB on-the-go full-speed (OTG_FS) 28.3 OTG_FS functional description Figure 302. OTG full-speed block diagram Cortex-M3 USB Interrupt USB2.0 Power& OTG FS Clock UTMIFS Core CTRL USB duspend System clock USB clock USB Clock at 48 MHz domain domain Universal serial bus 1.25 Kbytes USB data FIFOs...
Page 825: Otg Dual Role Device (Drd)
USB on-the-go full-speed (OTG_FS) RM0008 the physical support to USB connectivity. The full-speed OTG PHY includes the following components: • FS/LS transceiver module used by both host and device. It directly drives transmission and reception on the single-ended USB lines. •...
Page 826: Id Line Detection
RM0008 USB on-the-go full-speed (OTG_FS) 28.4.1 ID line detection The host or peripheral (the default) role is assumed depending on the ID input pin. The ID line status is determined on plugging in the USB, depending on which side of the USB cable is connected to the micro-AB receptacle.
Page 827: Usb Peripheral
USB on-the-go full-speed (OTG_FS) RM0008 28.5 USB peripheral This section gives the functional description of the OTG_FS in the USB peripheral mode. The OTG_FS works as an USB peripheral in the following circumstances: • OTG B-Peripheral – OTG B-device default state if B-side of USB cable is plugged in •...
Page 828: Peripheral States
RM0008 USB on-the-go full-speed (OTG_FS) 28.5.2 Peripheral states Powered state The V input detects the B-Session valid voltage by which the USB peripheral is allowed to enter the powered state (see USB2.0 par9.1). The OTG_FS then automatically connects the DP pull-up resistor to signal full-speed device connection to the host and generates the session request interrupt (SRQINT bit in OTG_FS_GINTSTS) to notify the powered state.
Page 829: Peripheral Endpoints
USB on-the-go full-speed (OTG_FS) RM0008 28.5.3 Peripheral endpoints The OTG_FS core instantiates the following USB endpoints: • Control endpoint 0: – Bidirectional and handles control messages only – Separate set of registers to handle in and out transactions – Proper control (OTG_FS_DIEPCTL0/OTG_FS_DOEPCTL0), transfer configuration (OTG_FS_DIEPTSIZ0/OTG_FS_DIEPTSIZ0), and status-interrupt (OTG_FS_DIEPINTx/)OTG_FS_DOEPINT0) registers.
Page 830 RM0008 USB on-the-go full-speed (OTG_FS) Endpoint control • The following endpoint controls are available to the application through the device endpoint-x IN/OUT control register (DIEPCTLx/DOEPCTLx): – Endpoint enable/disable – Endpoint activate in current configuration – Program USB transfer type (isochronous, bulk, interrupt) –...
Page 831: Usb Host
USB on-the-go full-speed (OTG_FS) RM0008 The peripheral core provides the following status checks and interrupt generation: • Transfer completed interrupt, indicating that data transfer was completed on both the application (AHB) and USB sides • Setup stage has been done (control-out only) •...
Page 832: Srp-Capable Host
RM0008 USB on-the-go full-speed (OTG_FS) Figure 305. USB host-only connection 1. STMPS2141STR needed only if the application has to support a V powered device. A basic power switch can be used if 5 V are available on the application board. 28.6.1 SRP-capable host SRP support is available through the SRP capable bit in the global USB configuration...
Page 833 USB on-the-go full-speed (OTG_FS) RM0008 Host detection of a peripheral connection If SRP or HNP are enabled, even if USB peripherals or B-devices can be attached at any time, the OTG_FS will not detect any bus connection until the end of the V sensing over 4.75 V).
Page 834: Host Channels
RM0008 USB on-the-go full-speed (OTG_FS) 28.6.3 Host channels The OTG_FS core instantiates 8 host channels. Each host channel supports an USB host transfer (USB pipe). The host is not able to support more than 8 transfer requests at the same time. If more than 8 transfer requests are pending from the application, the host controller driver (HCD) must re-allocate channels when they become available from previous duty, that is, after receiving the transfer completed and channel halted interrupts.
Page 835: Host Scheduler
USB on-the-go full-speed (OTG_FS) RM0008 corresponding bits in the HAINT and GINTSTS registers. The mask bits for each interrupt source of each channel are also available in the OTG_FS_HCINTMSK-x register. • The host core provides the following status checks and interrupt generation: –...
Page 836: Sof Trigger
RM0008 USB on-the-go full-speed (OTG_FS) PTXQSAV bits in the OTG_FS_HNPTXSTS register or NPTQXSAV bits in the OTG_FS_HNPTXSTS register. 28.7 SOF trigger Figure 306. SOF connectivity STM32F105xx STM32F107xx SOF pulse output, to external audio control VBUS PA11 ITR1 pulse PA12 SOFgen TIM2 PA10 ai17120...
Page 837: Power Options
USB on-the-go full-speed (OTG_FS) RM0008 register (SOFOUTEN bit in OTG_FS_GCCFG). The SOF pulse signal is also internally connected to the TIM2 input trigger, so that the input capture feature, the output compare feature and the timer can be triggered by the SOF pulse. The TIM2 connection is enabled . The end of periodic frame interrupt (GINTSTS/EOPF) is used to notify the application when 80%, 85%, 90% or 95% of the time frame interval elapsed depending on the periodic frame interval field in the device configuration register (PFIVL bit in OTG_FS_DCFG).
Page 838: Dynamic Update Of The Otg_Fs_Hfir Register
RM0008 USB on-the-go full-speed (OTG_FS) To save dynamic power, the USB data FIFO is clocked only when accessed by the OTG_FS core. 28.9 Dynamic update of the OTG_FS_HFIR register The USB core embeds a dynamic trimming capability of micro-SOF framing period in host mode allowing to synchronize an external device with the micro-SOF frames.
Page 839: Peripheral Fifo Architecture
USB on-the-go full-speed (OTG_FS) RM0008 28.11 Peripheral FIFO architecture Figure 308. Device-mode FIFO address mapping and AHB FIFO access mapping Single data FIFO DIEPTXF2[31:16] IN endpoint Tx FIFO #n Dedicated Tx Tx FIFO #n DFIFO push access packet FIFO #n control DIEPTXFx[15:0] from AHB (optional)
Page 840: Peripheral Tx Fifos
RM0008 USB on-the-go full-speed (OTG_FS) 28.11.2 Peripheral Tx FIFOs The core has a dedicated FIFO for each IN endpoint. The application configures FIFO sizes by writing the non periodic transmit FIFO size register (OTG_FS_TX0FSIZ) for IN endpoint0 and the device IN endpoint transmit FIFOx registers (DIEPTXFx) for IN endpoint-x. 28.12 Host FIFO architecture Figure 309.
Page 841: Host Tx Fifos
USB on-the-go full-speed (OTG_FS) RM0008 28.12.2 Host Tx FIFOs The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs are used as transmit buffers to hold the data (payload of the transmit packet) to be transmitted over the USB.
Page 842: Host Mode
RM0008 USB on-the-go full-speed (OTG_FS) Transmit FIFO RAM allocation: the minimum RAM space required for each IN Endpoint Transmit FIFO is the maximum packet size for that particular IN endpoint. Note: More space allocated in the transmit IN Endpoint FIFO results in better performance on the USB.
Page 843: Otg_Fs Interrupts
USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS to fill in the available RAM space at best regardless of the current USB sequence. With these features: • The application gains good margins to calibrate its intervention in order to optimize the CPU bandwidth usage: –...
Page 844: Otg_Fs Control And Status Registers
RM0008 USB on-the-go full-speed (OTG_FS) Figure 310. Interrupt hierarchy Interrupt Global interrupt mask (Bit 0) AHB configuration register 22 21 31 30 29 28 27 26 25 24 23 20 19 18 17:10 2 1 0 Core interrupt mask Core interrupt register register interrupt...
Page 845: Csr Memory Map
USB on-the-go full-speed (OTG_FS) RM0008 CSRs are classified as follows: • Core global registers • Host-mode registers • Host global registers • Host port CSRs • Host channel-specific registers • Device-mode registers • Device global registers • Device endpoint-specific registers •...
Page 846: Table 201. Core Global Control And Status Registers (Csrs)
RM0008 USB on-the-go full-speed (OTG_FS) Figure 311. CSR memory map 0000h Core global CSRs (1 Kbyte) 0400h Host mode CSRs (1 Kbyte) 0800h Device mode CSRs (1.5 Kbyte) 0E00h Power and clock gating CSRs (0.5 Kbyte) 1000h Device EP 0/Host channel 0 FIFO (4 Kbyte) 2000h Device EP1/Host channel 1 FIFO (4 Kbyte) 3000h...
Page 847: Table 202. Host-Mode Control And Status Registers (Csrs)
USB on-the-go full-speed (OTG_FS) RM0008 Table 201. Core global control and status registers (CSRs) (continued) Address Acronym Register name offset OTG_FS_GRXSTSR 0x01C OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) on page 866 OTG_FS_GRXSTSP 0x020 OTG_FS_GRXFSIZ 0x024 OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ) on page 867 OTG_FS Host non-periodic transmit FIFO size register OTG_FS_HNPTXFSIZ/...
Page 848: Table 203. Device-Mode Control And Status Registers
RM0008 USB on-the-go full-speed (OTG_FS) Table 202. Host-mode control and status registers (CSRs) (continued) Offset Acronym Register name address 0x500 0x520 OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) OTG_FS_HCCHARx (x = 0..7, where x = Channel_number) on page 878 0x6E0h OTG_FS Host channel-x interrupt register (OTG_FS_HCINTx) (x = 0..7, OTG_FS_HCINTx 508h where x = Channel_number) on page 879...
Page 849 USB on-the-go full-speed (OTG_FS) RM0008 Table 203. Device-mode control and status registers (continued) Offset Acronym Register name address 0x920 0x940 OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, OTG_FS_DIEPCTLx where x = Endpoint_number) on page 891 0xAE0 OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) OTG_FS_DIEPINTx 0x908 (x = 0..3, where x = Endpoint_number) on page 898...
Page 850: Otg_Fs Global Registers
RM0008 USB on-the-go full-speed (OTG_FS) Table 204. Data FIFO (DFIFO) access register map FIFO access register section Address range Access Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access 0x1000–0x1FFC Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access 0x2000–0x2FFC Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access...
Page 851 USB on-the-go full-speed (OTG_FS) RM0008 Bits 31:20 Reserved, must be kept at reset value. Bit 19 BSVLD: B-session valid Indicates the device mode transceiver status. 0: B-session is not valid. 1: B-session is valid. In OTG mode, you can use this bit to determine if the device is connected or disconnected. Note: Only accessible in device mode.
Page 852 RM0008 USB on-the-go full-speed (OTG_FS) Bit 8 HNGSCS: Host negotiation success The core sets this bit when host negotiation is successful. The core clears this bit when the HNP Request (HNPRQ) bit in this register is set. 0: Host negotiation failure 1: Host negotiation success Note: Only accessible in device mode.
Page 853 USB on-the-go full-speed (OTG_FS) RM0008 Bit 18 ADTOCHG: A-device timeout change The core sets this bit to indicate that the A-device has timed out while waiting for the B-device to connect. Note: Accessible in both device and host modes. Bit 17 HNGDET: Host negotiation detected The core sets this bit when it detects a host negotiation request on the USB.
Page 854 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS AHB configuration register (OTG_FS_GAHBCFG) Address offset: 0x008 Reset value: 0x0000 0000 This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming.
Page 855 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS USB configuration register (OTG_FS_GUSBCFG) Address offset: 0x00C Reset value: 0x0000 0A00 This register can be used to configure the core after power-on or a changing to host mode or device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the AHB or the USB.
Page 856 RM0008 USB on-the-go full-speed (OTG_FS) Bit 9 HNPCAP: HNP-capable The application uses this bit to control the OTG_FS controller’s HNP capabilities. 0: HNP capability is not enabled. 1: HNP capability is enabled. Note: Accessible in both device and host modes. Bit 8 SRPCAP: SRP-capable The application uses this bit to control the OTG_FS controller’s SRP capabilities.
Page 857 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS reset register (OTG_FS_GRSTCTL) Address offset: 0x10 Reset value: 0x2000 0000 The application uses this register to reset various hardware features inside the core. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TXFNUM Reserved Bit 31 AHBIDL: AHB master idle...
Page 858 RM0008 USB on-the-go full-speed (OTG_FS) Bit 2 FCRST: Host frame counter reset The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent SOF sent out by the core has a frame number of 0. Note: Only accessible in host mode.
Page 859 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS core interrupt register (OTG_FS_GINTSTS) Address offset: 0x014 Reset value: 0x0400 0020 This register interrupts the application for system-level events in the current mode (device mode or host mode). Some of the bits in this register are valid only in host mode, while others are valid in device mode only.
Page 860 RM0008 USB on-the-go full-speed (OTG_FS) Bit 25 HCINT: Host channels interrupt The core sets this bit to indicate that an interrupt is pending on one of the channels of the core (in host mode). The application must read the OTG_FS_HAINT register to determine the exact number of the channel on which the interrupt occurred, and then read the corresponding OTG_FS_HCINTx register to determine the exact cause of the interrupt.
Page 861 USB on-the-go full-speed (OTG_FS) RM0008 Bit 14 ISOODRP: Isochronous OUT packet dropped interrupt The core sets this bit when it fails to write an isochronous OUT packet into the RxFIFO because the RxFIFO does not have enough space to accommodate a maximum size packet for the isochronous OUT endpoint.
Page 862 RM0008 USB on-the-go full-speed (OTG_FS) Bit 3 SOF: Start of frame In host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is transmitted on the USB. The application must write a 1 to this bit to clear the interrupt. In device mode, in the core sets this bit to indicate that an SOF token has been received on the USB.
Page 863 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS interrupt mask register (OTG_FS_GINTMSK) Address offset: 0x018 Reset value: 0x0000 0000 This register works with the Core interrupt register to interrupt the application. When an interrupt bit is masked, the interrupt associated with that bit is not generated. However, the Core Interrupt (OTG_FS_GINTSTS) register bit corresponding to that interrupt is still set.
Page 864 RM0008 USB on-the-go full-speed (OTG_FS) Bits 23:22 Reserved, must be kept at reset value. Bit 21 IPXFRM: Incomplete periodic transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in host mode. IISOOXFRM: Incomplete isochronous OUT transfer mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode.
Page 865 USB on-the-go full-speed (OTG_FS) RM0008 Bit 11 USBSUSPM: USB suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bit 10 ESUSPM: Early suspend mask 0: Masked interrupt 1: Unmasked interrupt Note: Only accessible in device mode. Bits 9:8 Reserved, must be kept at reset value.
Page 866 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS Receive status debug read/OTG status read and pop registers (OTG_FS_GRXSTSR/OTG_FS_GRXSTSP) Address offset for Read: 0x01C Address offset for Pop: 0x020 Reset value: 0x0000 0000 A read to the Receive status debug read register returns the contents of the top of the Receive FIFO.
Page 867 USB on-the-go full-speed (OTG_FS) RM0008 Bits 31:25 Reserved, must be kept at reset value. Bits 24:21 FRMNUM: Frame number This is the least significant 4 bits of the frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. Bits 20:17 PKTSTS: Packet status Indicates the status of the received packet 0001: Global OUT NAK (triggers an interrupt)
Page 868 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS Host non-periodic transmit FIFO size register (OTG_FS_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_FS_DIEPTXF0) Address offset: 0x028 Reset value: 0x0000 0200 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 NPTXFD/TX0FD NPTXFSA/TX0FSA r/rw...
Page 869 USB on-the-go full-speed (OTG_FS) RM0008 Bit 31 Reserved, must be kept at reset value. Bits 30:24 NPTXQTOP: Top of the non-periodic transmit request queue Entry in the non-periodic Tx request queue that is currently being processed by the MAC. Bits 30:27: Channel/endpoint number Bits 26:25: –...
Page 870 RM0008 USB on-the-go full-speed (OTG_FS) Bit 18 VBUSASEN: Enable the V sensing “A” device 0: V sensing “A” disabled 1: V sensing “A” enabled Bit 17 Reserved, must be kept at reset value. Bit 16 PWRDWN: Power down Used to activate the transceiver in transmission/reception 0: Power down active 1: Power down deactivated (“Transceiver active”) Bits 15:0 Reserved, must be kept at reset value.
Page 871: Host-Mode Registers
USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXFx) (x = 1..3, where x is the FIFO_number) Address offset: 0x104 + (FIFO_number – 1) × 0x04 Reset value: 0x02000400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INEPTXFD INEPTXSA Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth...
Page 872 RM0008 USB on-the-go full-speed (OTG_FS) Bits 1:0 FSLSPCS: FS/LS PHY clock select When the core is in FS host mode 01: PHY clock is running at 48 MHz Others: Reserved When the core is in LS host mode 00: Reserved 01: Select 48 MHz PHY clock frequency 10: Select 6 MHz PHY clock frequency 11: Reserved...
Page 873 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS Host frame number/frame time remaining register (OTG_FS_HFNUM) Address offset: 0x408 Reset value: 0x0000 3FFF This register indicates the current frame number. It also indicates the time remaining (in terms of the number of PHY clocks) in the current frame. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 FTREM FRNUM...
Page 874 RM0008 USB on-the-go full-speed (OTG_FS) Bits 23:16 PTXQSAV: Periodic transmit request queue space available Indicates the number of free locations available to be written in the periodic transmit request queue. This queue holds both IN and OUT requests. 00: Periodic transmit request queue is full 01: 1 location available 10: 2 locations available bxn: n locations available (0 ≤...
Page 875 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS Host all channels interrupt mask register (OTG_FS_HAINTMSK) Address offset: 0x418 Reset value: 0x0000 0000 The host all channel interrupt mask register works with the host all channel interrupt register to interrupt the application when an event occurs on a channel. There is one interrupt mask bit per channel, up to a maximum of 16 bits.
Page 876 RM0008 USB on-the-go full-speed (OTG_FS) Bits 16:13 PTCTL: Port test control The application writes a nonzero value to this field to put the port into a Test mode, and the corresponding pattern is signaled on the port. 0000: Test mode disabled 0001: Test_J mode 0010: Test_K mode 0011: Test_SE0_NAK mode...
Page 877 USB on-the-go full-speed (OTG_FS) RM0008 Bit 5 POCCHNG: Port overcurrent change The core sets this bit when the status of the Port overcurrent active bit (bit 4) in this register changes. Bit 4 POCA: Port overcurrent active Indicates the overcurrent condition of the port. 0: No overcurrent condition 1: Overcurrent condition Bit 3 PENCHNG: Port enable/disable change...
Page 878 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS Host channel-x characteristics register (OTG_FS_HCCHARx) (x = 0..7, where x = Channel_number) Address offset: 0x500 + (Channel_number × 0x20) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 MCNT EPNUM MPSIZ...
Page 879 USB on-the-go full-speed (OTG_FS) RM0008 Bit 15 EPDIR: Endpoint direction Indicates whether the transaction is IN or OUT. 0: OUT 1: IN Bits 14:11 EPNUM: Endpoint number Indicates the endpoint number on the device serving as the data source or sink. Bits 10:0 MPSIZ: Maximum packet size Indicates the maximum packet size of the associated endpoint.
Page 880 RM0008 USB on-the-go full-speed (OTG_FS) Bit 2 Reserved, must be kept at reset value. Bit 1 CHH: Channel halted Indicates the transfer completed abnormally either because of any USB transaction error or in response to disable request by the application. Bit 0 XFRC: Transfer completed Transfer completed normally without any errors.
Page 881 USB on-the-go full-speed (OTG_FS) RM0008 Bit 2 Reserved, must be kept at reset value. Bit 1 CHHM: Channel halted mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed mask 0: Masked interrupt 1: Unmasked interrupt OTG_FS Host channel-x transfer size register (OTG_FS_HCTSIZx) (x = 0..7, where x = Channel_number) Address offset: 0x510 + (Channel_number ×...
Page 882: Device-Mode Registers
RM0008 USB on-the-go full-speed (OTG_FS) 28.16.4 Device-mode registers OTG_FS device configuration register (OTG_FS_DCFG) Address offset: 0x800 Reset value: 0x0220 0000 This register configures the core in device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw rw rw...
Page 883 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device control register (OTG_FS_DCTL) Address offset: 0x804 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value.
Page 884: Table 206. Minimum Duration For Soft Disconnect
RM0008 USB on-the-go full-speed (OTG_FS) Bit 2 GINSTS: Global IN NAK status 0: A handshake is sent out based on the data availability in the transmit FIFO. 1: A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
Page 885 USB on-the-go full-speed (OTG_FS) RM0008 Bit 3 EERR: Erratic error The core sets this bit to report any erratic errors. Due to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is generated to the application with Early suspend bit of the OTG_FS_GINTSTS register (ESUSP bit in OTG_FS_GINTSTS).
Page 886 RM0008 USB on-the-go full-speed (OTG_FS) Bit 3 TOM: Timeout condition mask (Non-isochronous endpoints) 0: Masked interrupt 1: Unmasked interrupt Bit 2 Reserved, must be kept at reset value. Bit 1 EPDM: Endpoint disabled interrupt mask 0: Masked interrupt 1: Unmasked interrupt Bit 0 XFRCM: Transfer completed interrupt mask 0: Masked interrupt 1: Unmasked interrupt...
Page 887 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device all endpoints interrupt register (OTG_FS_DAINT) Address offset: 0x818 Reset value: 0x0000 0000 When a significant event occurs on an endpoint, a OTG_FS_DAINT register interrupts the application using the Device OUT endpoints interrupt bit or Device IN endpoints interrupt bit of the OTG_FS_GINTSTS register (OEPINT or IEPINT in OTG_FS_GINTSTS, respectively).
Page 888 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK) Address offset: 0x81C Reset value: 0x0000 0000 The OTG_FS_DAINTMSK register works with the Device endpoint interrupt register to interrupt the application when an event occurs on a device endpoint. However, the OTG_FS_DAINT register bit corresponding to that interrupt is still set.
Page 889 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device V pulsing time register (OTG_FS_DVBUSPULSE) Address offset: 0x082C Reset value: 0x0000 05B8 This register specifies the V pulsing time during SRP. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DVBUSP Reserved rw rw rw rw rw rw rw rw rw rw rw rw...
Page 890 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0) Address offset: 0x900 Reset value: 0x0000 0000 This section describes the OTG_FS_DIEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 TXFNUM EPTYP MPSIZ...
Page 891 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status 1: The core is transmitting NAK handshakes on this endpoint. When this bit is set, either by the application or core, the core stops transmitting data, even if there are data available in the TxFIFO.
Page 892 RM0008 USB on-the-go full-speed (OTG_FS) Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt.
Page 893 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status It indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there are data available in the TxFIFO.
Page 894 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device control OUT endpoint 0 control register (OTG_FS_DOEPCTL0) Address offset: 0xB00 Reset value: 0x0000 8000 This section describes the OTG_FS_DOEPCTL0 register. Nonzero control endpoints use registers for endpoints 1–3. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EPTYP MPSIZ Reserved...
Page 895 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit, the core stops receiving data, even if there is space in the RxFIFO to accommodate the incoming packet.
Page 896 RM0008 USB on-the-go full-speed (OTG_FS) Bit 30 EPDIS: Endpoint disable The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint disabled interrupt.
Page 897 USB on-the-go full-speed (OTG_FS) RM0008 Bit 17 NAKSTS: NAK status Indicates the following: 0: The core is transmitting non-NAK handshakes based on the FIFO status. 1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
Page 898 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device endpoint-x interrupt register (OTG_FS_DIEPINTx) (x = 0..3, where x = Endpoint_number) Address offset: 0x908 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events.
Page 899 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device endpoint-x interrupt register (OTG_FS_DOEPINTx) (x = 0..3, where x = Endpoint_number) Address offset: 0xB08 + (Endpoint_number × 0x20) Reset value: 0x0000 0080 This register indicates the status of an endpoint with respect to USB- and AHB-related events.
Page 900 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device IN endpoint 0 transfer size register (OTG_FS_DIEPTSIZ0) Address offset: 0x910 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the endpoint enable bit in the device control endpoint 0 control registers (EPENA in OTG_FS_DIEPCTL0), the core modifies this register.
Page 901 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device OUT endpoint 0 transfer size register (OTG_FS_DOEPTSIZ0) Address offset: 0xB10 Reset value: 0x0000 0000 The application must modify this register before enabling endpoint 0. Once endpoint 0 is enabled using the Endpoint enable bit in the OTG_FS_DOEPCTL0 registers (EPENA bit in OTG_FS_DOEPCTL0), the core modifies this register.
Page 902 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS device endpoint-x transfer size register (OTG_FS_DIEPTSIZx) (x = 1..3, where x = Endpoint_number) Address offset: 0x910 + (Endpoint_number × 0x20) Reset value: 0x0000 0000 The application must modify this register before enabling the endpoint. Once the endpoint is enabled using the Endpoint enable bit in the OTG_FS_DIEPCTLx registers (EPENA bit in OTG_FS_DIEPCTLx), the core modifies this register.
Page 903 USB on-the-go full-speed (OTG_FS) RM0008 OTG_FS device IN endpoint transmit FIFO status register (OTG_FS_DTXFSTSx) (x = 0..3, where x = Endpoint_number) Address offset for IN endpoints: 0x918 + (Endpoint_number × 0x20) This read-only register contains the free space information for the Device IN endpoint TxFIFO. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INEPTFSAV Reserved...
Page 904: Otg_Fs Power And Clock Gating Control Register
RM0008 USB on-the-go full-speed (OTG_FS) STUPCNT: SETUP packet count Applies to control OUT Endpoints only. This field specifies the number of back-to-back SETUP data packets the endpoint can receive. 01: 1 packet 10: 2 packets 11: 3 packets Bit 28:19 PKTCNT: Packet count Indicates the total number of USB packets that constitute the Transfer Size amount of data for this endpoint.
Page 905: Otg_Fs Register Map
USB on-the-go full-speed (OTG_FS) RM0008 28.16.6 OTG_FS register map The table below gives the USB OTG register map and reset values. Table 207. OTG_FS register map and reset values Offset Register OTG_FS_GOT GCTL 0x000 Reserved Reserved Reserved Reset value OTG_FS_GOT GINT 0x004 Reserved...
Page 906 RM0008 USB on-the-go full-speed (OTG_FS) Table 207. OTG_FS register map and reset values (continued) Offset Register OTG_FS_GRXF RXFD 0x024 Reserved Reset value OTG_FS_HNPT XFSIZ/ NPTXFD/TX0FD NPTXFSA/TX0FSA OTG_FS_DIEP 0x028 TXF0 Reset value OTG_FS_HNPT NPTXQTOP NPTQXSAV NPTXFSAV XSTS 0x02C Reset value OTG_FS_ GCCFG 0x038 Reserved...
Page 907 USB on-the-go full-speed (OTG_FS) RM0008 Table 207. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCC MCNT EPNUM MPSIZ HAR2 0x540 Reset value OTG_FS_HCC MCNT EPNUM MPSIZ HAR3 0x560 Reset value OTG_FS_HCC MCNT EPNUM MPSIZ HAR4 0x580 Reset value OTG_FS_HCC MCNT EPNUM...
Page 908 RM0008 USB on-the-go full-speed (OTG_FS) Table 207. OTG_FS register map and reset values (continued) Offset Register OTG_FS_HCIN TMSK1 0x52C Reserved Reset value OTG_FS_HCIN TMSK2 0x54C Reserved Reset value OTG_FS_HCIN TMSK3 0x56C Reserved Reset value OTG_FS_HCIN TMSK4 0x58C Reserved Reset value OTG_FS_HCIN TMSK5 0x5AC...
Page 909 USB on-the-go full-speed (OTG_FS) RM0008 Table 207. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DCFG 0x800 Reserved Reset value OTG_FS_DCTL 0x804 Reserved Reset value OTG_FS_DSTS FNSOF 0x808 Reserved Reserved Reset value OTG_FS_DIEP 0x810 Reserved Reset value OTG_FS_DOEP 0x814 Reserved Reset value OTG_FS_DAIN...
Page 910 RM0008 USB on-the-go full-speed (OTG_FS) Table 207. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEP TXFNUM MPSIZ CTL2 0x940 Reserved Reset value TG_FS_DTXFS INEPTFSAV 0x958 Reserved Reset value OTG_FS_DIEP TXFNUM MPSIZ CTL3 0x960 Reserved Reset value TG_FS_DTXFS INEPTFSAV 0x978 Reserved Reset value...
Page 911 USB on-the-go full-speed (OTG_FS) RM0008 Table 207. OTG_FS register map and reset values (continued) Offset Register OTG_FS_DIEPI 0x968 Reserved Reset value OTG_FS_DOEP INT0 0xB08 Reserved Reset value OTG_FS_DOEP INT1 0xB28 Reserved Reset value OTG_FS_DOEP INT2 0xB48 Reserved Reset value OTG_FS_DOEP INT3 0xB68 Reserved...
Page 912: Otg_Fs Programming Model
RM0008 USB on-the-go full-speed (OTG_FS) 28.17 OTG_FS programming model 28.17.1 Core initialization The application must perform the core initialization sequence. If the cable is connected during power-up, the current mode of operation bit in the OTG_FS_GINTSTS (CMOD bit in OTG_FS_GINTSTS) reflects the mode. The OTG_FS controller enters host mode when an “A”...
Page 913: Host Initialization
USB on-the-go full-speed (OTG_FS) RM0008 28.17.2 Host initialization To initialize the core as host, the application must perform the following steps: Program the HPRTINT in the OTG_FS_GINTMSK register to unmask Program the OTG_FS_HCFG register to select full-speed host Program the PPWR bit in OTG_FS_HPRT to 1. This drives V on the USB.
Page 914: Host Programming Model
RM0008 USB on-the-go full-speed (OTG_FS) register to determine the enumeration speed and perform the steps listed in Endpoint initialization on enumeration completion on page 931. At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint 0.
Page 915: Figure 312. Transmit Fifo Write Task
USB on-the-go full-speed (OTG_FS) RM0008 When an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received for an IN or OUT channel. The application must be able to receive other interrupts (DTERR, Nak, Data, TXERR) for the same channel before receiving the halt. When a DISCINT (Disconnect Device) interrupt in OTG_FS_GINTSTS is received.
Page 916: Figure 313. Receive Fifo Read Task
RM0008 USB on-the-go full-speed (OTG_FS) • Reading the receive FIFO The application must ignore all packet statuses other than IN data packet (bx0010). Figure 313. Receive FIFO read task Start RXFLVL interrupt ? Unmask RXFLVL Mask RXFLVL Unmask RXFLVL interrupt interrupt interrupt Read the received...
Page 917 USB on-the-go full-speed (OTG_FS) RM0008 SETUP transaction operates in the same way but has only one packet. The assumptions are: – The application is attempting to send two maximum-packet-size packets (transfer size = 1, 024 bytes). – The non-periodic transmit FIFO can hold two packets (128 bytes for FS). –...
Page 918: Figure 314. Normal Bulk/Control Out/Setup And Bulk/Control In Transactions
RM0008 USB on-the-go full-speed (OTG_FS) Figure 314. Normal bulk/control OUT/SETUP and bulk/control IN transactions Application Host Device init_reg(ch _1) Non-Periodic Request init _reg(ch_2) Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set _ch_en (ch _2) ch_1 write_tx_fifo (ch_1) ch_2 set _ch_en...
Page 919 USB on-the-go full-speed (OTG_FS) RM0008 De-allocate Channel else if (STALL) Transfer Done = 1 Unmask CHH Disable Channel else if (NAK or TXERR ) Rewind Buffer Pointers Unmask CHH Disable Channel if (TXERR) Increment Error Count Unmask ACK else Reset Error Count else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3))
Page 920 RM0008 USB on-the-go full-speed (OTG_FS) Reset Error Count Mask ACK else if (TXERR or BBERR or STALL) Unmask CHH Disable Channel if (TXERR) Increment Error Count Unmask ACK else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel...
Page 921: Figure 315. Bulk/Control In Transactions
USB on-the-go full-speed (OTG_FS) RM0008 Figure 315. Bulk/control IN transactions Application Host Device init_reg(ch _1) Non-Periodic Request init _reg(ch_2) Queue write_tx_fifo Assume that this queue (ch_1) can hold 4 entries. set _ch_en (ch _2) ch_1 write_tx_fifo ch_2 (ch_1) set _ch_en ch_1 (ch _2) ch_2...
Page 922 RM0008 USB on-the-go full-speed (OTG_FS) The core generates the RXFLVL interrupt for the transfer completion status entry in the receive FIFO. The application must read and ignore the receive packet status when the receive packet status is not an IN data packet (PKTSTS in GRXSTSR ≠ 0b0010). The core generates the XFRC interrupt as soon as the receive packet status is read.
Page 923: Figure 316. Normal Interrupt Out/In Transactions
USB on-the-go full-speed (OTG_FS) RM0008 Figure 316. Normal interrupt OUT/IN transactions Application Host Device init _reg(ch_1) init_reg(ch _2) Periodic Request Queue Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en ch_1 (ch_2) ch_2 (micro) frame init _reg(ch_1) write_tx_fifo (ch_1) RXFLVL interrupt read_rx_sts...
Page 924 RM0008 USB on-the-go full-speed (OTG_FS) Disable Channel if (STALL) Transfer Done = 1 else if (NAK or TXERR) Rewind Buffer Pointers Reset Error Count Mask ACK Unmask CHH Disable Channel else if (CHH) Mask CHH if (Transfer Done or (Error_count == 3)) De-allocate Channel else Re-initialize Channel (in next b_interval - 1 Frame)
Page 925 USB on-the-go full-speed (OTG_FS) RM0008 else if (STALL or FRMOR or NAK or DTERR or BBERR) Mask ACK Unmask CHH Disable Channel if (STALL or BBERR) Reset Error Count Transfer Done = 1 else if (!FRMOR) Reset Error Count else if (TXERR) Increment Error Count Unmask ACK...
Page 926 RM0008 USB on-the-go full-speed (OTG_FS) • Interrupt IN transactions The assumptions are: – The application is attempting to receive one packet (up to 1 maximum packet size) in every frame, starting with odd (transfer size = 1 024 bytes). – The receive FIFO can hold at least one maximum-packet-size packet and two status Words per packet (1 031 bytes).
Page 927 USB on-the-go full-speed (OTG_FS) RM0008 • Isochronous OUT transactions A typical isochronous OUT operation is shown in Figure 317. The assumptions are: – The application is attempting to send one packet every frame (up to 1 maximum packet size), starting with an odd frame. (transfer size = 1 024 bytes). –...
Page 928: Figure 317. Normal Isochronous Out/In Transactions
RM0008 USB on-the-go full-speed (OTG_FS) Figure 317. Normal isochronous OUT/IN transactions Host Device Application init _reg(ch_1) init_reg(ch _2) Periodic Request Queue Assume that this queue write_tx_fifo can hold 4 entries. (ch_1) set_ch_en ch_1 (ch_2) ch_2 (micro) frame init _reg(ch_1) write_tx_fifo (ch_1) RXFLVL interrupt read_rx_sts...
Page 929 USB on-the-go full-speed (OTG_FS) RM0008 else if (CHH) Mask CHH De-allocate Channel Code sample: Isochronous IN Unmask (TXERR/XFRC/FRMOR/BBERR) if (XFRC or FRMOR) if (XFRC and (OTG_FS_HCTSIZx.PKTCNT == 0)) Reset Error Count De-allocate Channel else Unmask CHH Disable Channel else if (TXERR or BBERR) Increment Error Count Unmask CHH Disable Channel...
Page 930 RM0008 USB on-the-go full-speed (OTG_FS) • Isochronous IN transactions The assumptions are: – The application is attempting to receive one packet (up to 1 maximum packet size) in every frame starting with the next odd frame (transfer size = 1 024 bytes). –...
Page 931: Device Programming Model
USB on-the-go full-speed (OTG_FS) RM0008 the channel. Port babble occurs if the core continues to receive data from the device at EOF2 (the end of frame 2, which is very close to SOF). When OTG_FS controller detects a packet babble, it stops writing data into the Rx buffer and waits for the end of packet (EOP).
Page 932 RM0008 USB on-the-go full-speed (OTG_FS) At this point, the device is ready to receive SOF packets and is configured to perform control transfers on control endpoint 0. Endpoint initialization on SetAddress command This section describes what the application must do when it receives a SetAddress command in a SETUP packet.
Page 933: Operational Model
USB on-the-go full-speed (OTG_FS) RM0008 In the endpoint to be deactivated, clear the USB active endpoint bit in the OTG_FS_DIEPCTLx register (for IN or bidirectional endpoints) or the OTG_FS_DOEPCTLx register (for OUT or bidirectional endpoints). Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint, which results in a timeout on the USB.
Page 934: Figure 318. Receive Fifo Packet Read
RM0008 USB on-the-go full-speed (OTG_FS) completed. After this entry is popped from the receive FIFO, the core asserts a Transfer Completed interrupt on the specified OUT endpoint. After the data payload is popped from the receive FIFO, the RXFLVL interrupt (OTG_FS_GINTSTS) must be unmasked.
Page 935 USB on-the-go full-speed (OTG_FS) RM0008 determine the correct number of SETUP packets received in the Setup stage of a control transfer. – STUPCNT = 3 in OTG_FS_DOEPTSIZx The application must always allocate some extra space in the Receive data FIFO, to be able to receive up to three SETUP packets on a control endpoint.
Page 936: Figure 319. Processing A Setup Packet
RM0008 USB on-the-go full-speed (OTG_FS) Figure 319. Processing a SETUP packet Wait for STUP in OTG_FS_DOEPINTx rem_supcnt = rd_reg(DOEPTSIZx) setup_cmd[31:0] = mem[4 – 2 * rem_supcnt] setup_cmd[63:32] = mem[5 – 2 * rem_supcnt] Find setup cmd type Read ctrl-rd/wr/2 stage Write 2-stage setup_np_in_pkt...
Page 937 USB on-the-go full-speed (OTG_FS) RM0008 To stop receiving any kind of data in the receive FIFO, the application must set the Global OUT NAK bit by programming the following field: – SGONAK = 1 in OTG_FS_DCTL Wait for the assertion of the GONAKEFF interrupt in OTG_FS_GINTSTS. When asserted, this interrupt indicates that the core has stopped receiving any type of data except SETUP packets.
Page 938 RM0008 USB on-the-go full-speed (OTG_FS) Before setting up an OUT transfer, the application must allocate a buffer in the memory to accommodate all data to be received as part of the OUT transfer. For OUT transfers, the transfer size field in the endpoint’s transfer size register must be a multiple of the maximum packet size of the endpoint, adjusted to the Word boundary.
Page 939 USB on-the-go full-speed (OTG_FS) RM0008 The OUT data transfer completed pattern for an OUT endpoint is written to the receive FIFO on one of the following conditions: – The transfer size is 0 and the packet count is 0 – The last OUT data packet written to the receive FIFO is a short packet (0 ≤...
Page 940 RM0008 USB on-the-go full-speed (OTG_FS) OTG_FS_DOEPTSIZx with the data PID of the last isochronous OUT data packet read from the receive FIFO. Application programming sequence: Program the OTG_FS_DOEPTSIZx register for the transfer size and the corresponding packet count Program the OTG_FS_DOEPCTLx register with the endpoint characteristics and set the Endpoint Enable, ClearNAK, and Even/Odd frame bits.
Page 941 USB on-the-go full-speed (OTG_FS) RM0008 (IISOOXFRM in OTG_FS_GINTSTS), indicating that an XFRC interrupt (in OTG_FS_DOEPINTx) is not asserted on at least one of the isochronous OUT endpoints. At this point, the endpoint with the incomplete transfer remains enabled, but no active transfers remain in progress on this endpoint on the USB. Application programming sequence: Asserting the IISOOXFRM interrupt (OTG_FS_GINTSTS) indicates that in the current frame, at least one isochronous OUT endpoint has an incomplete transfer.
Page 942: Figure 320. Bulk Out Transaction
RM0008 USB on-the-go full-speed (OTG_FS) Examples This section describes and depicts some fundamental transfer types and scenarios. • Bulk OUT transaction Figure 320 depicts the reception of a single Bulk OUT Data packet from the USB to the AHB and describes the events involved in the process. Figure 320.
Page 943 USB on-the-go full-speed (OTG_FS) RM0008 IN data transfers • Packet write This section describes how the application writes data packets to the endpoint FIFO when dedicated transmit FIFOs are enabled. The application can either choose the polling or the interrupt mode. –...
Page 944 RM0008 USB on-the-go full-speed (OTG_FS) To stop transmitting any data on a particular IN endpoint, the application must set the IN NAK bit. To set this bit, the following field must be programmed. – SNAK = 1 in OTG_FS_DIEPCTLx Wait for assertion of the INEPNE interrupt in OTG_FS_DIEPINTx. This interrupt indicates that the core has stopped transmitting data on the endpoint.
Page 945 USB on-the-go full-speed (OTG_FS) RM0008 • Generic non-periodic IN data transfers Application requirements: Before setting up an IN transfer, the application must ensure that all data to be transmitted as part of the IN transfer are part of a single buffer. For IN transfers, the Transfer Size field in the Endpoint Transfer Size register denotes a payload that constitutes multiple maximum-packet-size packets and a single short packet.
Page 946 RM0008 USB on-the-go full-speed (OTG_FS) handshake, the packet count for the endpoint is decremented by one, until the packet count is zero. The packet count is not decremented on a timeout. For zero length packets (indicated by an internal zero length flag), the core sends out a zero-length packet for the IN token and decrements the packet count field.
Page 947 USB on-the-go full-speed (OTG_FS) RM0008 The application can only schedule data transfers one frame at a time. (MCNT – 1) × MPSIZ ≤ XFERSIZ ≤ MCNT × MPSIZ – – PKTCNT = MCNT (in OTG_FS_DIEPTSIZx) – If XFERSIZ < MCNT × MPSIZ, the last data packet of the transfer is a short packet.
Page 948 RM0008 USB on-the-go full-speed (OTG_FS) Application programming sequence: Program the OTG_FS_DIEPCTLx register with the endpoint characteristics and set the CNAK and EPENA bits. Write the data to be transmitted in the next frame to the transmit FIFO. Asserting the ITTXFE interrupt (in OTG_FS_DIEPINTx) indicates that the application has not yet written all data to be transmitted to the transmit FIFO.
Page 949 USB on-the-go full-speed (OTG_FS) RM0008 Application programming sequence: The application can ignore the IN token received when TxFIFO empty interrupt in OTG_FS_DIEPINTx on any isochronous IN endpoint, as it eventually results in an incomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS). Assertion of the incomplete isochronous IN transfer interrupt (in OTG_FS_GINTSTS) indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints.
Page 950: Worst Case Response Time
RM0008 USB on-the-go full-speed (OTG_FS) application receives this interrupt, it must set the STALL bit in the corresponding endpoint control register, and clear this interrupt. 28.17.7 Worst case response time When the OTG_FS controller acts as a device, there is a worst case response time for any tokens that follow an isochronous OUT.
Page 951: Otg Programming Model
USB on-the-go full-speed (OTG_FS) RM0008 Figure 321. TRDT max timing case 50ns 100ns 150ns 200ns HCLK PCLK tkn_rcvd dsynced_tkn_rcvd spr_read spr_addr spr_rdata srcbuf_push srcbuf_rdata 5 Clocks ai15680 28.17.8 OTG programming model The OTG_FS controller is an OTG device supporting HNP and SRP. When the core is connected to an “A”...
Page 952: Figure 322. A-Device Srp
RM0008 USB on-the-go full-speed (OTG_FS) Figure 322. A-device SRP Suspend DRV_VBUS VBUS_VALID pulsing A_VALID Connect Data line pulsing ai15681 1. DRV_VBUS = V drive signal to the PHY VBUS_VALID = V valid signal from PHY A_VALID = A-peripheral V level signal to PHY D+ = Data plus line D- = Data minus line To save power, the application suspends and turns off port power when the bus is idle...
Page 953: Figure 323. B-Device Srp
USB on-the-go full-speed (OTG_FS) RM0008 B-device session request protocol The application must set the SRP-capable bit in the Core USB configuration register. This enables the OTG_FS controller to initiate SRP as a B-device. SRP is a means by which the OTG_FS controller can request a new session from the host.
Page 954: Figure 324. A-Device Hnp
RM0008 USB on-the-go full-speed (OTG_FS) discharge time can be obtained from the transceiver vendor and varies from one transceiver to another. The USB OTG core informs the PHY to speed up V discharge. The application initiates SRP by writing the session request bit in the OTG Control and status register.
Page 955 USB on-the-go full-speed (OTG_FS) RM0008 and status register to indicate to the OTG_FS controller that the B-device supports HNP. When it has finished using the bus, the application suspends by writing the Port suspend bit in the host port control and status register. When the B-device observes a USB suspend, it disconnects, indicating the initial condition for HNP.
Page 956: Figure 325. B-Device Hnp
RM0008 USB on-the-go full-speed (OTG_FS) Figure 325. B-device HNP OTG core Device Host Device Suspend 2 Connect Reset Traffic Traffic DPPULLDOWN DMPULLDOWN ai15684 1. DPPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DP line inside the PHY. DMPULLDOWN = signal from core to PHY to enable/disable the pull-down on the DM line inside the PHY.
Page 957 USB on-the-go full-speed (OTG_FS) RM0008 negotiation success. The application must read the current Mode bit in the Core interrupt register (OTG_FS_GINTSTS) to determine host mode operation. The application sets the reset bit (PRST in OTG_FS_HPRT) and the OTG_FS controller issues a USB reset and enumerates the A-device for data traffic. The OTG_FS controller continues the host role of initiating traffic, and when done, suspends the bus by writing the Port suspend bit in the host port control and status register.
Page 958: Ethernet (Eth): Media Access Control (Mac) With Dma Controller
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Ethernet (ETH): media access control (MAC) with DMA controller Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
Page 959: Mac Core Features
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 29.2.1 MAC core features • Supports 10/100 Mbit/s data transfer rates with external PHY interfaces • IEEE 802.3-compliant MII interface to communicate with an external Fast Ethernet • Supports both full-duplex and half-duplex operations –...
Page 960: Dma Features
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Store-and-Forward mode • Option to forward under-sized good frames • Supports statistics by generating pulses for frames dropped or corrupted (due to overflow) in the Receive FIFO • Supports Store and Forward mechanism for transmission to the MAC core •...
Page 961: Ethernet Pins
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 29.3 Ethernet pins Table 208 shows the MAC signals and the corresponding MII/RMII default or remapped signals. It also indicates the pins onto which the signals are input or output, and the pin configuration.
Page 962: Ethernet Functional Description: Smi, Mii And Rmii
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Table 208. Ethernet pin configuration (continued) MAC signals MII default MII remap RMII default RMII remap Pin configuration ETH_MII_RXD2 RXD2 PD11 Floating input (reset state) ETH_MII_RXD3 RXD3 PD12 Floating input (reset state) 29.4 Ethernet functional description: SMI, MII and RMII The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated...
Page 963: Table 209. Management Frame Format
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 The application can select one of the 32 PHYs and one of the 32 registers within any PHY and send control data or receive status information. Only one register in one PHY can be addressed at any given time.
Page 964: Figure 328. Mdio Timing And Frame Structure - Write Cycle
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The management frame consists of eight fields: • Preamble: each transaction (read or write) can be initiated with the preamble field that corresponds to 32 contiguous logic one bits on the MDIO line with 32 corresponding cycles on MDC.
Page 965: Table 210. Clock Range
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 SMI read operation When the user sets the MII Busy bit in the Ethernet MAC MII address register (ETH_MACMIIAR) with the MII Write bit at 0, the SMI initiates a read operation in the PHY registers by transferring the PHY address and the register address in PHY.
Page 966: Media-Independent Interface: Mii
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller 29.4.2 Media-independent interface: MII The media-independent interface (MII) defines the interconnection between the MAC sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s. Figure 330. Media independent interface signals •...
Page 967: Table 211. Tx Interface Signal Encoding
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 deasserted and MII_RX_ER is asserted, a specific MII_RXD[3:0] value is used to transfer specific information from the PHY (see Table 212). • MII_RX_DV: receive data valid indicates that the PHY is presenting recovered and decoded nibbles on the MII for reception.
Page 968: Reduced Media-Independent Interface: Rmii
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 331. MII clock sources 29.4.3 Reduced media-independent interface: RMII The reduced media-independent interface (RMII) specification reduces the pin count between the microcontroller Ethernet peripheral and the external Ethernet in 10/100 Mbit/s. According to the IEEE 802.3u standard, an MII contains 16 pins for data and control.
Page 969: Mii/Rmii Selection
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 RMII clock sources As described in the RMII clock sources section, the STM32F10xxxSTM32F107xx could provide this 50 MHz clock signal on its MCO output pin and you then have to configure this output value through PLL configuration.
Page 970: Ethernet Functional Description: Mac 802.3
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller To save a pin, the two input clock signals, RMII_REF_CK and MII_RX_CLK, are multiplexed on the same GPIO pin. 29.5 Ethernet functional description: MAC 802.3 The IEEE 802.3 International Standard for local area networks (LANs) employs the CSMA/CD (carrier sense multiple access with collision detection) as the access method.
Page 971: Figure 335. Address Field Format
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 336 Figure 337 describe the frame structure (untagged and tagged) that includes the following fields: • Preamble: 7-byte field used for synchronization purposes (PLS circuitry) Hexadecimal value: 55-55-55-55-55-55-55 Bit pattern: 01010101 01010101 01010101 01010101 01010101 01010101 01010101 (right-to-left bit transmission) •...
Page 972 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller hexadecimal). This constant field is used to distinguish tagged and untagged MAC frames. – 2-byte field containing the Tag control information field subdivided as follows: a 3- bit user priority, a canonical format indicator (CFI) bit and a 12-bit VLAN Identifier. The length of the tagged MAC frame is extended by 4 bytes by the QTag Prefix.
Page 973: Figure 336. Mac Frame Format
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 336. MAC frame format 7 bytes Preamble 1 byte 6 bytes Destination address Bytes within frame transmitted 6 bytes Source address top to bottom 2 bytes MAC client length/type MAC client data 46-1500 bytes 4 bytes...
Page 974: Mac Frame Transmission
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller 29.5.2 MAC frame transmission The DMA controls all transactions for the transmit path. Ethernet frames read from the system memory are pushed into the FIFO by the DMA. The frames are then popped out and transferred to the MAC core.
Page 975 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 The CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The encoding is defined by the following polynomial. G x ( ) Transmit protocol The MAC controls the operation of Ethernet frame transmission. It performs the following functions to meet the IEEE 802.3/802.3z specifications.
Page 976 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller configured for 96 bit times, the MAC follows the rule of deference specified in Section 4.2.3.2.1 of the IEEE 802.3 specification. The MAC resets its IFG counter if a carrier is detected during the first two-thirds (64-bit times for all IFG values) of the IFG interval.
Page 977 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 frame is being transmitted. As soon as the first frame has been transferred and the status is received from the MAC, it is pushed to the DMA. If the DMA has already completed sending the second packet to the FIFO, the second transmission must wait for the status of the first packet before proceeding to the next frame.
Page 978 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller is set in the ETH_ETH_DMAOMR register). If the core is configured for Threshold (cut- through) mode, the Transmit checksum offload is bypassed. You must make sure the Transmit FIFO is deep enough to store a complete frame before that frame is transferred to the MAC Core transmitter.
Page 979 Ethernet (ETH): media access control (MAC) with DMA controller RM0008 error, it inserts an IPv4 header checksum if the Ethernet Type field indicates an IPv4 payload. • TCP/UDP/ICMP checksum The TCP/UDP/ICMP checksum processes the IPv4 or IPv6 header (including extension headers) and determines whether the encapsulated payload is TCP, UDP or ICMP.
Page 980: Figure 338. Transmission Bit Order
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 338. Transmission bit order Bibit stream MII_TXD[3:0] Nibble stream ai15632 MII/RMII transmit timing diagrams Figure 339. Transmission with no collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15631 DocID13902 Rev 15 980/1128 1064...
Page 981: Mac Frame Reception
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 340. Transmission with collision MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CS MII_COL ai15651 Figure 341 shows a frame transmission in MII and RMII. Figure 341. Frame transmission in MMI and RMII modes MII_RX_CLK MII_TX_EN MII_TXD[3:0]...
Page 982 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller packet has been transferred. Upon completion of the EOF frame transfer, the status word is popped out and sent to the DMA controller. In Rx FIFO Store-and-forward mode (configured by the RSF bit in the ETH_DMAOMR register), a frame is read out only after being written completely into the Receive FIFO.
Page 983: Table 213. Frame Statuses
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 type (Ethernet Type field) and the IP header version, or when the received frame does not have enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20 bytes are available in an IPv4 or IPv6 header).
Page 984 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller the frame is dropped and the Rx Status Word is immediately updated (with zero frame length, CRC error and Runt Error bits set), indicating the filter fail. In Ethernet power down mode, all received frames are dropped, and are not forwarded to the application.
Page 985: Figure 342. Receive Bit Order
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Receive status word At the end of the Ethernet frame reception, the MAC outputs the receive status to the application (DMA). The detailed description of the receive status is the same as for bits[31:0] in RDES0, given in RDES0: Receive descriptor Word0 on page 1016.
Page 986: Figure 343. Reception With No Error
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 343. Reception with no error MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15634 Figure 344. Reception with errors MII_RX_CLK MII_RX_DV MII_RXD[3:0] PREAMBLE MII_RX_ERR ai15635 Figure 345. Reception with false carrier indication MII_RX_CLK MII_RX_DV MII_RXD[3:0]...
Page 987: Mac Interrupts
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 29.5.4 MAC interrupts Interrupts can be generated from the MAC core as a result of various events. The ETH_MACSR register describes the events that can cause an interrupt from the MAC core.
Page 988 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller is set to 1, the unicast frame is said to have passed the Hash filter; otherwise, the frame has failed the Hash filter. Note: This CRC is a 32-bit value coded by the following polynomial (for more details refer to Section 29.5.3: MAC frame reception): G x ( )
Page 989: Table 214. Destination Address Filtering
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Inverse filtering operation For both destination and source address filtering, there is an option to invert the filter-match result at the final output. These are controlled by the DAIF and SAIF bits in the Frame filter register, respectively.
Page 990: Mac Loopback Mode
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Table 215. Source address filtering Frame type SAIF SA filter operation Pass all frames Pass status on perfect/Group filter match but do not drop frames that fail Unicast Fail status on perfect/group filter match but do not drop frame Pass on perfect/group filter match and drop frames that fail Fail on perfect/group filter match and drop frames that fail 29.5.6...
Page 991: Power Management: Pmt
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Received frames are considered “good” if none of the following errors exists: + CRC error + Runt Frame (shorter than 64 bytes) + Alignment error (in 10/ 100 Mbit/s only) + Length error (non-Type frames only) + Out of Range (non-Type frames only, longer than maximum size) + MII_RXER Input error...
Page 992: Figure 347. Wakeup Frame Filter Register
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Figure 347. Wakeup frame filter register Filter 0 Byte Mask Wakeup frame filter reg0 Filter 1 Byte Mask Wakeup frame filter reg1 Filter 2 Byte Mask Wakeup frame filter reg2 Filter 3 Byte Mask Wakeup frame filter reg3 Filter 3...
Page 993 SRAM. To disable the Ethernet DMA, clear the ST bit and the SR bit (for the transmit DMA and the receive DMA, respectively) in the ETH_DMAOMR register.
Page 994: Precision Time Protocol (Ieee1588 Ptp)
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller Disable the transmit DMA and wait for any previous frame transmissions to complete. These transmissions can be detected when the transmit interrupt ETH_DMASR register[0] is received. Disable the MAC transmitter and MAC receiver by clearing the RE and TE bits in the ETH_MACCR configuration register.
Page 995: Figure 348. Networked Time Synchronization
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Figure 348. Networked time synchronization Master clock time Slave clock time Sync message Data at slave clock Follow_up message containing value of t1 Delay_Req message Delay_Resp message containing value of t4 time ai15669 The master broadcasts PTP Sync messages to all its nodes.
Page 996 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller be greater than or equal to the resolution of time stamp counter. The synchronization accuracy target between the master node and the slaves is around 100 ns. The generation, update and modification of the System Time are described in the Section : System Time correction methods.
Page 997: Figure 349. System Time Update Using The Fine Correction Method
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a high- precision frequency multiplier or divider. Figure 349 shows this algorithm. Figure 349. System time update using the Fine correction method Addend register Addend update Accumulator register...
Page 998 RM0008 Ethernet (ETH): media access control (MAC) with DMA controller The algorithm is as follows: • At time MasterSyncTime (n) the master sends the slave clock a Sync message. The slave receives this message when its local clock is SlaveClockTime (n) and computes MasterClockTime (n) as: MasterClockTime (n) = MasterSyncTime (n) + MasterToSlaveDelay (n) •...
Page 999: Figure 350. Ptp Trigger Output To Tim2 Itr1 Connection
Ethernet (ETH): media access control (MAC) with DMA controller RM0008 Programming steps for system time update in the Coarse correction method To synchronize or update the system time in one process (coarse correction method), perform the following steps: Write the offset (positive or negative) in the Time stamp update high and low registers. Set bit 3 (TSSTU) in the Time stamp control register.
Page 1000: Ethernet Functional Description: Dma Controller Operation
RM0008 Ethernet (ETH): media access control (MAC) with DMA controller PTP pulse-per-second output signal This PTP pulse output is used to check the synchronization between all nodes in the network. To be able to test the difference between the local slave clock and the master reference clock, both clocks were given a pulse-per-second (PPS) output signal that may be connected to an oscilloscope if necessary.

This manual is also suitable for:

Stm32f107 series Stm32f102 series Stm32f103 series Stm32f105 seriesStm32f101 series