Interrupts; Dma Request Mapping; Table 77. Dma Interrupt Requests; Figure 50. Dma1 Request Mapping - ST STM32F101 series Reference Manual

RM0008
13.3.6

Interrupts

An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for
each DMA channel. Separate interrupt enable bits are available for flexibility.
Half-transfer
Transfer complete
Transfer error
Note: In high-density and XL-density devices, DMA2 Channel4 and DMA2 Channel5 interrupts
are mapped onto the same interrupt vector. In connectivity line devices, DMA2 Channel4
and DMA2 Channel5 interrupts have separate interrupt vectors. All other DMA1 and DMA2
Channel interrupts have their own interrupt vector.
13.3.7

DMA request mapping

DMA1 controller
The 7 requests from the peripherals (TIMx[1,2,3,4], ADC1, SPI1, SPI/I2S2, I2Cx[1,2] and
USARTx[1,2,3]) are simply logically ORed before entering the DMA1, this means that only
one request must be enabled at a time. Refer to
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.

Table 77. DMA interrupt requests

Interrupt event
DocID13902 Rev 15
Direct memory access controller (DMA)
Event flag
HTIF
TCIF
TEIF
Figure 50: DMA1 request
Enable Control bit
HTIE
TCIE
TEIE
mapping.
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