Dma Functional Description; Dma Transactions; Figure 49. Dma Block Diagram In Low-, Medium- High- And Xl-Density Devices - ST STM32F101 series Reference Manual

Advanced arm-based 32-bit mcus

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Table of Contents

Direct memory access controller (DMA)

Reset & clock control

1. The DMA2 controller is available only in high-density and XL-density devices.

1. ADC3, SPI/I2S3, UART4, SDIO, TIM5, TIM6, DAC, TIM7, TIM8 DMA requests are available only in high-

density devices

DMA functional description

The DMA controller performs direct memory transfer by sharing the system bus with the

-M3 core. The DMA request may stop the CPU access to the system bus for some

bus cycles, when the CPU and DMA are targeting the same destination (memory or

peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half

of the system bus bandwidth (both to memory and peripheral) for the CPU.

After an event, the peripheral sends a request signal to the DMA Controller. The DMA

controller serves the request depending on the channel priorities. As soon as the DMA

Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA

Controller. The peripheral releases its request as soon as it gets the Acknowledge from the

DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller

release the Acknowledge. If there are more requests, the peripheral can initiate the next

transaction.

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