Timer Synchronization; Figure 139. Control Circuit In External Clock Mode 2 + Trigger Mode; Figure 140. Master/Slave Timer Example - ST STM32F101 series Reference Manual

General-purpose timers (TIM2 to TIM5)
Counter clock = CK_CNT = CK_PSC
15.3.15

Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 140: Master/Slave timer example
the master mode selection blocks.
Using one timer as prescaler for another
Clock
Prescaler
For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Figure 140. To do this:
•
Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
•
To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in
slave mode using ITR0 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=000).
•
Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).
• Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer 2.
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Figure 139. Control circuit in external clock mode 2 + trigger mode

TI1
CEN/CNT_EN
ETR
Counter register
TIF

Figure 140. Master/Slave timer example

TIM1
MMS
Master
UEV
mode
control
Counter
DocID13902 Rev 15
34
presents an overview of the trigger selection and
TS SMS
Slave
TRGO1 ITR0
mode
control
Input
trigger
selection
35 36
TIM2
CK_PSC
Counter
Prescaler
RM0008